Design and analysis of electrostatic doped Schottky barrier CNTFET based low power SRAM

Abstract In recent years, much emphasis is given for low power memory design by reducing leakage power. Carbon nanotube field effect transistor (CNTFET) based static random access memory (SRAM) provides better stability along with low static power consumption due to variable bandgap and threshold voltage as function of diameter. Electrostatic doped Schottky barrier carbon nanotube field effect transistor (ED-SBCNTFET) accounts for much low leakage current and hence can be used for low power SRAM design. This paper proposes a novel design of ED-SBCNTFET based low power SRAM which consists of additional polarity gates. 6-T SRAM cell is designed and simulated in HSPICE for both conventional CNTFET and ED-SBCNTFET. SRAM performance is analyzed on the basis of various figures of merit i.e. stability and power dissipation. ED-SBCNTFET SRAM shows advantage of low power over conventional CNTFET SRAM without loss of stability. Furthermore, SRAM is designed for smaller diameter which gives ultra low power cell with minute change in stability. Lastly dual chirality scheme is implemented and analyzed for ED-SBCNTFET 6-T SRAM cell.

[1]  M. J. Kumar,et al.  Bipolar Charge-Plasma Transistor: A Novel Three Terminal Device , 2012, IEEE Transactions on Electron Devices.

[2]  M. J. Kumar,et al.  Doping-Less Tunnel Field Effect Transistor: Design and Investigation , 2013, IEEE Transactions on Electron Devices.

[3]  S. Selberherr,et al.  Numerical Analysis of Coaxial Double Gate Schottky Barrier Carbon Nanotube Field Effect Transistors , 2004, 2004 Abstracts 10th International Workshop on Computational Electronics.

[4]  Jawar Singh,et al.  PVT-Aware Design of Dopingless Dynamically Configurable Tunnel FET , 2015, IEEE Transactions on Electron Devices.

[5]  P. McEuen,et al.  Single-walled carbon nanotube electronics , 2002 .

[6]  S. Tans,et al.  Room-temperature transistor based on a single carbon nanotube , 1998, Nature.

[7]  Pravin N. Kondekar,et al.  A novel dynamically configurable electrostatically doped silicon nanowire impact ionization MOS , 2015 .

[8]  Anuj Pushkarna,et al.  Comparison of performance parameters of SRAM designs in 16nm CMOS and CNTFET technologies , 2010, 23rd IEEE International SOC Conference.

[9]  José G. Delgado-Frias,et al.  SRAM leakage in CMOS, FinFET and CNTFET technologies: leakage in 8t and 6t sram cells , 2012, GLSVLSI '12.

[10]  B. Raj,et al.  Circuit Compatible Model for Electrostatic Doped Schottky Barrier CNTFET , 2016, Journal of Electronic Materials.

[11]  H. Dai,et al.  High performance n-type carbon nanotube field-effect transistors with chemically doped contacts. , 2004, Nano letters.

[12]  Alain C. Diebold,et al.  2012 Updates to the International Technology Roadmap for Semiconductors (ITRS) Metrology Chapter | NIST , 2013 .

[13]  Hiroshi Iwai,et al.  Roadmap for 22nm and beyond (Invited Paper) , 2009 .

[14]  Yong-Bin Kim,et al.  A new SRAM cell design using CNTFETs , 2008, 2008 International SoC Design Conference.

[15]  J. Knoch,et al.  High-performance carbon nanotube field-effect transistor with tunable polarities , 2005, IEEE Transactions on Nanotechnology.

[16]  Chao Lu,et al.  Power efficient SRAM design with integrated bit line charge pump , 2016 .

[17]  A. Shaker,et al.  Gate dielectric constant engineering for suppression of ambipolar conduction in CNTFETs , 2015 .

[18]  S. Wind,et al.  Carbon nanotube electronics , 2002, Digest. International Electron Devices Meeting,.

[19]  S. Dasgupta,et al.  Nanoscale FinFET Based SRAM Cell Design: Analysis of Performance Metric, Process Variation, Underlapped FinFET, and Temperature Effect , 2011, IEEE Circuits and Systems Magazine.

[20]  Mohamed I. Elmasry,et al.  Design and optimization of multithreshold CMOS (MTCMOS) circuits , 2003, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[21]  Mohamed I. Elmasry,et al.  Multi-Threshold CMOS Digital Circuits: Managing Leakage Power , 2003 .

[22]  Fabrizio Lombardi,et al.  Design and process variation analysis of CNTFET-based ternary memory cells , 2016, Integr..

[23]  Yong-Bin Kim,et al.  Design of a CNTFET-Based SRAM Cell by Dual-Chirality Selection , 2010, IEEE Transactions on Nanotechnology.

[24]  B. Raj,et al.  Analysis of electrostatic doped Schottky barrier carbon nanotube FET for low power applications , 2016, Journal of Materials Science: Materials in Electronics.

[25]  Payman Zarkesh-Ha,et al.  Comparison of variations in MOSFET versus CNFET in gigascale integrated systems , 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

[26]  Hiroshi Iwai,et al.  Roadmap for 22nm and beyond , 2009 .

[27]  C. Salm,et al.  The Charge Plasma P-N Diode , 2008, IEEE Electron Device Letters.

[28]  S. A. Abbasi,et al.  A high performance double gate dopingless metal oxide semiconductor field effect transistor , 2014, 2014 20th International Conference on Ion Implantation Technology (IIT).

[29]  P. B. Pillai,et al.  Are carbon nanotubes still a viable option for ITRS 2024? , 2013, 2013 IEEE International Electron Devices Meeting.

[30]  J. Chen,et al.  Self-aligned carbon nanotube transistors with novel chemical doping , 2004, IEDM Technical Digest. IEEE International Electron Devices Meeting, 2004..

[31]  Chao Lu,et al.  Charge recycling 8T SRAM design for low voltage robust operation , 2016 .

[32]  Tze-Chiang Chen,et al.  Overcoming research challenges for CMOS scaling: industry directions , 2006, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.