A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines

AVS technique for extremely scaled SoCs has been developed. To reduce design cost, we have developed a supply voltage control scheme employing universal delay line (UDL), rather than a replica delay line, for monitoring the critical path delay (TCRIT). The UDL can be used in any product without any need for customizing. In addition, averaging the results of distributed 4 monitors with a pitch of 3 mm in a chip can reduce errors due to within-die variation by half. With these techniques, proposed scheme produces equivalent or less error to TCRIT than does a conventional scheme that uses a single critical path replica as a delay monitor, even with simple monitor design. We have shown that 40-nm CMOS SoCs using our AVS can reduce active power by 27%.

[1]  Vivek De,et al.  Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors , 2002, VLSIC 2002.

[2]  Dragan Maksimovic,et al.  Closed-loop adaptive voltage scaling controller for standard-cell ASICs , 2002, ISLPED '02.

[3]  R. Thewes,et al.  Efficiency of body biasing in 90 nm CMOS for low power digital circuits , 2004 .

[4]  Manoj Sachdev,et al.  Variation-Aware Adaptive Voltage Scaling System , 2007, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[5]  J. Kim,et al.  An efficient digital sliding controller for adaptive power supply regulation , 2001, 2001 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.01CH37185).

[6]  Takahiro Seki,et al.  Dynamic voltage and frequency management for a low-power embedded microprocessor , 2005, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[7]  A. Inoue,et al.  Supply Voltage Adjustment Technique for Low Power Consumption and Its Application to SOCs with Multiple Threshold Voltage CMOS , 2006, 2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers..

[8]  Uming Ko,et al.  SmartReflex Power and Performance Management Technologies for 90 nm, 65 nm, and 45 nm Mobile Application Processors , 2010, Proceedings of the IEEE.

[9]  K. Takeda,et al.  Delay and power monitoring schemes for minimizing power consumption by means of supply and threshold voltage control in active and standby modes , 2006, IEEE Journal of Solid-State Circuits.

[10]  Soraya Ghiasi,et al.  A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.