A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines
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Yoshihiro Hayashi | Koichi Nose | Masayuki Mizuno | Masahiro Nomura | Toshiyuki Saito | Koichiro Noguchi | Tomohiro Iwashita | Yoshifumi Ikenaga | Shuji Suenaga | Hideo Sonohara | Yoshitaka Horikoshi | Yukio Ohdaira | Yoichiro Nishio | Miyuki Satou | Koji Nishida
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