Eh?Predictor: A Deep Learning Framework to Identify Detailed Routing Short Violations From a Placed Netlist

Detailed routing is one of the most challenging aspects of the physical design process. Many of the violations that occur during the detailed routing stage stem from the placement of the cells. In this paper, we propose a deep learning framework to identify short violations that can occur during detailed routing from a placed netlist. One of the advantages of our technique is that by using the proposed deep learning-based predictor, global routing is no longer required as frequently and hence the total runtime for place and route can be significantly reduced. In this paper, we discuss the proposed framework and the methodology for analyzing the extracted features. The experimental results show that the average sensitivity, specificity, and accuracy of Eh?Predictor is above 90%. In addition, we show that Eh?Predictor is up to 14 times faster than NCTUgr for smaller designs and up to 96 times faster for larger designs.

[1]  Evangeline F. Y. Young,et al.  Multivoltage Floorplan Design , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[2]  Andrew A. Kennings,et al.  Detailed routing violation prediction during placement using machine learning , 2017, 2017 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

[3]  Tao Huang,et al.  Ripple 2.0: High quality routability-driven placement via global router integration , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[4]  Jarrod A. Roy,et al.  CRISP: Congestion reduction by iterated spreading during placement , 2009, 2009 IEEE/ACM International Conference on Computer-Aided Design - Digest of Technical Papers.

[5]  Ismail Bustany,et al.  A Machine Learning Framework to Identify Detailed Routing Short Violations from a Placed Netlist , 2018, 2018 55th ACM/ESDA/IEEE Design Automation Conference (DAC).

[6]  David S. Johnson,et al.  Computers and Intractability: A Guide to the Theory of NP-Completeness , 1978 .

[7]  Cheng-Kok Koh,et al.  Optimization of placement solutions for routability , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[8]  Nadine Gottschalk,et al.  Vlsi Physical Design From Graph Partitioning To Timing Closure , 2016 .

[9]  Majid Sarrafzadeh,et al.  Predictable routing , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[10]  Ismail Bustany,et al.  ICCAD-2017 CAD contest in multi-deck standard cell legalization and benchmarks , 2017, 2017 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[11]  Dana Ron,et al.  An Experimental and Theoretical Comparison of Model Selection Methods , 1995, COLT '95.

[12]  Jimmy Ba,et al.  Adam: A Method for Stochastic Optimization , 2014, ICLR.

[13]  Sachin S. Sapatnekar,et al.  GLARE: Global and local wiring aware routability evaluation , 2012, DAC Design Automation Conference 2012.

[14]  Azadeh Davoodi,et al.  A Comparative Study of Local Net Modeling Using Machine Learning , 2018, ACM Great Lakes Symposium on VLSI.

[15]  Malgorzata Marek-Sadowska,et al.  Power/ground mesh area optimization using multigrid-based technique [IC design] , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[16]  Azadeh Davoodi,et al.  Congestion analysis for global routing via integer programming , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[17]  D. Chinnery,et al.  ISPD 2015 Benchmarks with Fence Regions and Routing Blockages for Detailed-Routing-Driven Placement , 2015, ISPD.

[18]  Iris Hui-Ru Jiang,et al.  Machine-Learning-Based Hotspot Detection Using Topological Classification and Critical Feature Extraction , 2015, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[19]  Li-C. Wang,et al.  Experience of Data Analytics in EDA and Test—Principles, Promises, and Challenges , 2017, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[20]  Hung-Ming Chen,et al.  A learning-based methodology for routability prediction in placement , 2018, 2018 International Symposium on VLSI Design, Automation and Test (VLSI-DAT).

[21]  J. Andres Torres,et al.  ICCAD-2012 CAD contest in fuzzy pattern matching for physical verification and benchmark suite , 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[22]  Seetha Hari,et al.  Learning From Imbalanced Data , 2019, Advances in Computer and Electrical Engineering.

[23]  David T. Westwick,et al.  Eh?Placer , 2016, ACM Trans. Design Autom. Electr. Syst..

[24]  Wilm E. Donath Complexity Theory and Design Automation , 1980, 17th Design Automation Conference.

[25]  Magdy S. Abadir,et al.  Design-Silicon Timing Correlation A Data Mining Perspective , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[26]  Kwang-Ting Cheng,et al.  Electronic Design Automation: Synthesis, Verification, and Test , 2009 .

[27]  Jin Hu,et al.  Progress and Challenges in VLSI Placement Research , 2012, Proceedings of the IEEE.

[28]  Iris Hui-Ru Jiang,et al.  Machine-learning-based hotspot detection using topological classification and critical feature extraction , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[29]  Nitesh V. Chawla,et al.  Editorial: special issue on learning from imbalanced data sets , 2004, SKDD.

[30]  Chris C. N. Chu,et al.  Pin Accessibility-Driven Detailed Placement Refinement , 2017, ISPD.

[31]  Chris C. N. Chu,et al.  IPR: An Integrated Placement and Routing Algorithm , 2007, 2007 44th ACM/IEEE Design Automation Conference.

[32]  Andrew A. Kennings,et al.  A Detailed Routing-Aware Detailed Placement Technique , 2015, 2015 IEEE Computer Society Annual Symposium on VLSI.