论文信息 - Parallel FPGA implementation of self-organizing maps

Parallel FPGA implementation of self-organizing maps

This paper presents an area-saving parallel implementation of a self-organizing map neural network (SOM) on FPGA. The purpose is to make available a finer grain of parallelism to be used in massively SIMD parallel SOM system architectures. We have handled a serial arithmetics (most significant bit first: MSBF and least significant bit first: LSBF), to process the different mathematical operations. Above all, our work has been oriented in such a way to get a light, easy to wear system for classification of vigilance states in humans from electroencephalographic (EEG) signals. The performances of our implementation in terms of area, speed and especially power consumption are highly satisfactory.

F. Alexandre | K. Ben Khalifa | B. Girau | M.H. Bedoui

[1] Paolo Ienne,et al. Bit-Serial Multipliers and Squarers , 1994, IEEE Trans. Computers.

[2] Michel Verleysen,et al. Analog implementation of a Kohonen map with on-chip learning , 1993, IEEE Trans. Neural Networks.

[3] Bernard Girau,et al. MLP computing and learning on FPGA using on-line arithmetic , 1999 .

[4] Patrick Thiran,et al. On modifications of Kohonen's feature map algorithm for an efficient parallel implementation , 1996, Proceedings of International Conference on Neural Networks (ICNN'96).

[5] K. Khalifa,et al. Analyse et classification des états de vigilance par réseaux de neurones , 2003 .