Fault-simulation based design error diagnosis for sequential circuits

This paper addresses the problem of locating design errors in a sequential circuit. For single-error circuits, we consider a signal ƒ as a potential error source only if the circuit can be completely rectified by re-synthesizing ƒ (i.e., changing the function of signal ƒ). In order to handle larger circuits, we do not rely on Binary Decision Diagram. Instead, we search for potential error sources by a modified sequential fault simulation process. The main contributions of this paper are two-fold: (1) we derive the necessary and sufficient condition of whether an erroneous input sequence (i.e., an input sequence producing erroneous responses) can be corrected by changing the function of a particular internal signal; and (2) we propose a modified fault simulation procedure to check this condition. Our approach does not rely on any error model, and thus, is suitable for general types of errors. Furthermore, it can be easily extended to identify multiple errors. Experimental results on ISCAS89 benchmark circuits are presented to demonstrate its capability.

[1]  K. A. Tamura,et al.  Locating Functional Errors in Logic Circuits , 1989, 26th ACM/IEEE Design Automation Conference.

[2]  Irith Pomeranz,et al.  A method for diagnosing implementation errors in synchronous sequential circuits and its implications on synthesis , 1993, Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference.

[3]  D. I. Cheng,et al.  Error Diagnosis for Transistor-Level Verification , 1994, 31st Design Automation Conference.

[4]  Olivier Coudert,et al.  Automating the diagnosis and the rectification of design errors with PRIAM , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[5]  Olivier Coudert,et al.  Automating the diagnosis and the rectification of design errors with PRIAM , 1989, ICCAD 1989.

[6]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[7]  Dominique Borrione,et al.  Design error diagnosis in sequential circuits , 1995, CHARME.

[8]  M. Marek-Sadowska,et al.  Logic synthesis for engineering change , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[9]  Magdy S. Abadir,et al.  Logic design verification via test generation , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  H. Al-Asaad,et al.  Design verification via simulation and automatic test pattern generation , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[11]  Wu-Tung Cheng,et al.  Differential Fault Simulation - A Fast Method Using Minimal Memory , 1989, 26th ACM/IEEE Design Automation Conference.

[12]  P. R. Stephan,et al.  SIS : A System for Sequential Circuit Synthesis , 1992 .

[13]  Masahiro Tomita,et al.  An algorithm for locating logic design errors , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[14]  Liaw Heh-Tyan,et al.  Efficient automatic diagnosis of digital circuits , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[15]  Ibrahim N. Hajj,et al.  A fast algorithm for locating and correcting simple design errors in VLSI digital circuits , 1997, Proceedings Great Lakes Symposium on VLSI.

[16]  Dominique Borrione,et al.  A method for automatic design error location and correction in combinational logic circuits , 1996, J. Electron. Test..

[17]  Irith Pomeranz,et al.  On correction of multiple design errors , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[18]  E BryantRandal Graph-Based Algorithms for Boolean Function Manipulation , 1986 .

[19]  Ibrahim N. Hajj,et al.  Logic design error diagnosis and correction , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[20]  Masahiro Fujita,et al.  Methods for automatic design error correction in sequential circuits , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[21]  Andreas Kuehlmann,et al.  The use of random simulation in formal verification , 1996, Proceedings International Conference on Computer Design. VLSI in Computers and Processors.

[22]  D. I. Cheng,et al.  ErrorTracer: a fault simulation-based approach to design error diagnosis , 1997, Proceedings International Test Conference 1997.