Techniques for Power and Process Variation Minimization
暂无分享,去创建一个
[1] Shekhar Borkar,et al. Obeying Moore's law beyond 0.18 micron [microprocessor design] , 2000, Proceedings of 13th Annual IEEE International ASIC/SOC Conference (Cat. No.00TH8541).
[2] James Tschanz,et al. Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors , 2002, DAC '02.
[3] H. Mizuno,et al. A 18 /spl mu/A-standby-current 1.8 V 200 MHz microprocessor with self substrate-biased data-retention mode , 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278).
[4] Bing J. Sheu,et al. BSIM: Berkeley short-channel IGFET model for MOS transistors , 1987 .
[5] Lawrence T. Clark,et al. An embedded 32-b microprocessor core for low-power and high-performance applications , 2001 .
[6] L.T. Clark. A high-voltage output buffer fabricated on a 2 V CMOS technology , 1999, 1999 Symposium on VLSI Circuits. Digest of Papers (IEEE Cat. No.99CH36326).
[7] S. Borkar,et al. Dynamic-sleep transistor and body bias for active leakage power control of microprocessors , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..
[8] James D. Meindl,et al. Impact of die-to-die and within-die parameter fluctuations on the maximum clock frequency distribution for gigascale integration , 2002, IEEE J. Solid State Circuits.
[9] Lawrence T. Clark,et al. Standby power management for a 0.18/spl mu/m microprocessor , 2002 .
[10] Kaushik Roy,et al. Technology scaling behavior of optimum reverse body bias for standby leakage power reduction in CMOS IC's , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).
[11] A. Alvandpour,et al. High-performance and low-power challenges for sub-70 nm microprocessor circuits , 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).
[12] Vivek De,et al. Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
[13] R.W. Brodersen,et al. A dynamic voltage scaled microprocessor system , 2000, IEEE Journal of Solid-State Circuits.
[14] David J. Frank,et al. Power-constrained CMOS scaling limits , 2002, IBM J. Res. Dev..
[15] P. Bai,et al. A high performance 180 nm generation logic technology , 1998, International Electron Devices Meeting 1998. Technical Digest (Cat. No.98CH36217).
[16] Young,et al. Dual Threshold Voltages And Substrate Bias: Keys To High Performance, Low Power, 0.1 /spl mu/m Logic Designs , 1997, 1997 Symposium on VLSI Technology.
[17] B. M. Gordon,et al. Supply and threshold voltage scaling for low power CMOS , 1997, IEEE J. Solid State Circuits.
[18] R. M. Swanson,et al. Ion-implanted complementary MOS transistors in low-voltage circuits , 1972 .
[19] J. Tschanz,et al. Design optimizations of a high performance microprocessor using combinations of dual-V/sub T/ allocation and transistor sizing , 2002, 2002 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.02CH37302).
[20] Shin'ichiro Mutoh,et al. 1-V power supply high-speed digital circuit technology with multithreshold-voltage CMOS , 1995, IEEE J. Solid State Circuits.
[21] Vivek De,et al. Effectiveness of reverse body bias for leakage control in scaled dual Vt CMOS ICs , 2001, ISLPED '01.
[22] S. Narendra,et al. 1.1 V 1 GHz communications router with on-chip body bias in 150 nm CMOS , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).