Evolvable Hardware Does Improve Design of Digital Combinational Circuits Performance

Evolvable Hardware (EH) is a new approach for designing digital circuits. In this paper, the effect of evolution variables for evolving digital combinational circuits has been considered. For this purpose, an extrinsic EH at gate level has been used. Computational effort and number of successful designs are used for evaluating the performance of evolved circuits. The effect of changing mutation rate, population size and circuit geometry on the performance of evolution has been analyzed. A 3-bit multiplier, a 7bit even parity generator, a 2-bit full adder and an 8 to 1 multiplexer are used as benchmark circuits. Finally, we proposed a new method for changing mutation rate. Simulation results demonstrate that using dynamic mutation rate can increase the acceptable range for mutation rate value. The increase in the acceptable range by using dynamic mutation rate is about 40 times for 3-bit multiplier, about 10 times for even parity generator, about 40 times for a 2-bit adder and about 16 times for an 8 to 1 multiplexer.

[1]  Terence C. Fogarty,et al.  Varying the Probability of Mutation in the Genetic Algorithm , 1989, ICGA.

[2]  Zbigniew Michalewicz,et al.  Adaptation in evolutionary computation: a survey , 1997, Proceedings of 1997 IEEE International Conference on Evolutionary Computation (ICEC '97).

[3]  E. Stomeo,et al.  Generalized Disjunction Decomposition for Evolvable Hardware , 2006, IEEE Transactions on Systems, Man, and Cybernetics, Part B (Cybernetics).

[4]  Ingo Rechenberg,et al.  Evolutionsstrategie : Optimierung technischer Systeme nach Prinzipien der biologischen Evolution , 1973 .

[5]  Garrison W. Greenwood,et al.  Introduction to Evolvable Hardware - A Practical Guide for Designing Self-Adaptive Systems , 2006 .

[6]  Mehrdad Salami,et al.  Evolvable hardware at function level , 1997, Proceedings of 1997 IEEE International Conference on Evolutionary Computation (ICEC '97).

[7]  Julian Francis Miller,et al.  The Automatic Acquisition, Evolution and Reuse of Modules in Cartesian Genetic Programming , 2008, IEEE Transactions on Evolutionary Computation.

[8]  R. Krohling,et al.  Evolving FPGA-based robot controllers using an evolutionary algorithm , 2002 .

[9]  Thomas Bäck,et al.  Intelligent Mutation Rate Control in Canonical Genetic Algorithms , 1996, ISMIS.

[10]  Tatiana Kalganova,et al.  Mutation Rate for Evolvable Hardware , 2007, IEC.

[11]  Joaquin Sitte,et al.  A gate-level model for morphogenetic evolvable hardware , 2004, Proceedings. 2004 IEEE International Conference on Field- Programmable Technology (IEEE Cat. No.04EX921).

[12]  Hans-Georg Beyer,et al.  The Theory of Evolution Strategies , 2001, Natural Computing Series.

[13]  Kwee-Bo Sim,et al.  Genetic programming of process decomposition strategies for evolvable hardware , 2000, Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware.

[14]  John R. Koza,et al.  The importance of reuse and development in evolvable hardware , 2003, NASA/DoD Conference on Evolvable Hardware, 2003. Proceedings..

[15]  W. Vent,et al.  Rechenberg, Ingo, Evolutionsstrategie — Optimierung technischer Systeme nach Prinzipien der biologischen Evolution. 170 S. mit 36 Abb. Frommann‐Holzboog‐Verlag. Stuttgart 1973. Broschiert , 1975 .

[16]  Garrison W. Greenwood,et al.  Introduction to evolvable hardware , 2006 .

[17]  Kurt Ammon.  The Automatic Acquisition of Proof Methods , 1988, AAAI.