论文信息 - A low voltage, 10-2550MHz, 0.15/spl mu/ CMOS, process and divider modulus independent PLL using zero-VT MOSFETs

A low voltage, 10-2550MHz, 0.15/spl mu/ CMOS, process and divider modulus independent PLL using zero-VT MOSFETs

This paper presents a current-mode, feed-forward loop filter PLL architecture that uses a bandgap referencing technique to achieve a process independent damping factor. It requires no external loop filter settings and provides divider modulus independent loop time constants through the usage of linear-N dependent charge-pump currents. A low voltage operation is achieved with extensive usage of zero-VT MOSFETs throughout the signal path, while maintaining a tight process control of the time constants with RC defined products. The frequency synthesizer specifications include: 10-2550 MHz frequency range, 1.5V digital/1V analog supply voltage, sub 1% T/sub osc/ rms jitter, 35 mW power dissipation and 800 /spl times/ 200 /spl mu/m/sup 2/ die area.

A. Maxim

[1] T. Frank,et al. Fully integrated CMOS phase-locked loop with 15 to 240 MHz locking range and /spl plusmn/50 ps jitter , 1995 .

[2] A. Maxim,et al. A low-jitter 125-1250-MHz process-independent and ripple-poleless 0.18-/spl mu/m CMOS PLL based on a sample-reset loop filter , 2001 .

[3] M. Bayer,et al. Cell based fully integrated CMOS frequency synthesizers , 1993, Proceedings of IEEE Custom Integrated Circuits Conference - CICC '93.

[4] J.G. Maneatis,et al. Low-jitter and process independent DLL and PLL based on self biased techniques , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[5] P.R. Gray,et al. A 1.4 GHz differential low-noise CMOS frequency synthesizer using a wideband PLL architecture , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).