Localization and Electrical Characterization of Interconnect Open Defects
暂无分享,去创建一个
R. Rodriguez-Montaes | D. Arumí | J. Figueras | W. Beverloo | D.K. de Vries | S. Eichenberger | P. Volf
[1] R Matick,et al. Transmission Lines for Digital and Communication Networks , 1969 .
[2] Wojciech Maly,et al. Testing oriented analysis of CMOS ICs with opens , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.
[3] W. Lukaszek,et al. Test chip based approach to automated diagnosis of CMOS yield problems , 1990 .
[4] J. Soden,et al. The use of light emission in failure analysis of CMOS ICs , 1990 .
[5] R. Glang. Defect size distribution in VLSI chips , 1991 .
[6] Jochen A. G. Jess,et al. A GENERIC METHOD TO DEVELOP A DEFECT MONITORING SYSTEM FOR IC PROCESSES , 1991, 1991, Proceedings. International Test Conference.
[7] Charles F. Hawkins,et al. THE BEHAVIOR AND TESTING IMPLICATIONS OF CMOS IC LOGIC GATE OPEN CIRCUITS , 1991, 1991, Proceedings. International Test Conference.
[8] Rosa Rodríguez-Montañés,et al. Bridging defects resistance measurements in a CMOS process , 1992, Proceedings International Test Conference 1992.
[9] C. Hess,et al. Test structure for the detection, localization and identification of short circuits with a high speed digital tester , 1992, ICMTS 92 Proceedings of the 1992 International Conference on Microelectronic Test Structures.
[10] C. Hess,et al. Modeling of real defect outlines and parameter extraction using a checkerboard test structure to localize defects , 1994 .
[11] M. E. Thomas,et al. Extraction of defect size distributions in an IC layer using test structure data , 1994 .
[12] A.V.S. Satya,et al. Microelectronic test structures for rapid automated contactless inline defect inspection , 1997 .
[13] O. S. Nakagawa,et al. Rapid characterization and modeling of pattern-dependent variation in chemical-mechanical polishing , 1998 .
[14] Charles Ching-Hsiang Hsu,et al. Design and simulation of addressable failure site test structure for IC process control monitor , 1999, 1999 International Symposium on VLSI Technology, Systems, and Applications. Proceedings of Technical Papers. (Cat. No.99TH8453).
[15] Edward J. McCluskey,et al. Testing for resistive opens and stuck opens , 2001, Proceedings International Test Conference 2001 (Cat. No.01CH37260).
[16] Christopher Hess,et al. Fast extraction of defect size distribution using a single layer short flow NEST structure , 2001 .
[17] Tae Hong Park. Characterization and modeling of pattern dependencies in copper interconnects for integrated circuits , 2002 .
[18] Rosa Rodríguez-Montañés,et al. Resistance characterization for weak open defects , 2002, IEEE Design & Test of Computers.
[19] Jayanthi Pallinti,et al. Design rule methodology to improve the manufacturability of the copper CMP process , 2002, Proceedings of the IEEE 2002 International Interconnect Technology Conference (Cat. No.02EX519).
[20] Sreejit Chakravarty,et al. Fault models for speed failures caused by bridges and opens , 2002, Proceedings 20th IEEE VLSI Test Symposium (VTS 2002).
[21] Anthony J. Walton,et al. Evaluation of sheet resistance and electrical linewidth measurement techniques for copper damascene interconnect , 2002 .
[22] Dirk K. de Vries,et al. Calibration of open interconnect yield models , 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.
[23] Yu Cao,et al. Modeling the electrical effects of metal dishing due to CMP for on-chip interconnect optimization , 2004, IEEE Transactions on Electron Devices.
[24] Y. Hamamura,et al. An advanced defect-monitoring test structure for electrical screening and defect localization , 2004, IEEE Transactions on Semiconductor Manufacturing.
[25] Ananta K. Majhi,et al. New test methodology for resistive open defect detection in memory address decoders , 2004, 22nd IEEE VLSI Test Symposium, 2004. Proceedings..
[26] K. Nikawa. How long can we succeed using the OBIRCH and its derivatives , 2004 .
[27] C. Spanos,et al. Dishing-radius model of copper CMP dishing effects , 2005, IEEE Transactions on Semiconductor Manufacturing.
[28] Lei He,et al. Case study and efficient modelling for variational chemical-mechanical planarisation , 2008, IET Circuits Devices Syst..