Mode Enabled Coprocessor for Precision Multipliers

Multiplication and division are the two elementary operations essential for the core computing process or for the arithmetic operation. These two operations are also the most critical functions carried out by the processors, as the multiplication requires more number of steps for the computation, limiting the overall performance of the system, and the division has the highest latency among all arithmetic operations. Thus, high performance multiplication and division algorithms/ architectures, if available, will considerably improve the speeds of processing system. Consequently, the need for faster processing of arithmetic operations, is continuously driving major improvements in processor technologies, as well as the search for new arithmetic algorithms. In the present paper alternate design for single and double precision multiplier processor is presented.

[1]  L. Sriraman.  FPGA IMPLEMENTATION OF HIGH PERFORMANCE MULTIPLIER USING SQUARER , 2012 .

[2]  M. Tull,et al.  High-speed complex number multiplier and inner-product processor , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

[3]  Rutuparna Panda,et al.  Speed Comparison of 16x16 Vedic Multipliers , 2011 .

[4]  Michael J. Schulte,et al.  A quadruple precision and dual double precision floating-point multiplier , 2003, Euromicro Symposium on Digital System Design, 2003. Proceedings..

[5]  José G. Delgado-Frias,et al.  A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance , 2008, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[6]  Metin Mete Özbilen,et al.  A single/double precision floating-point reciprocal unit design for multimedia applications , 2009 .

[7]  L. Ciminiera,et al.  Low cost serial multipliers for high-speed specialised processors , 1988 .

[8]  S. Akhter.  VHDL implementation of fast NxN multiplier based on vedic mathematic , 2007, 2007 18th European Conference on Circuit Theory and Design.

[9]  G. Marcus,et al.  A fully synthesizable single-precision, floating-point adder/substractor and multiplier in VHDL for general and educational use , 2004, Proceedings of the Fifth IEEE International Caracas Conference on Devices, Circuits and Systems, 2004..

[10]  Neil Burgess,et al.  A GaAs IEEE floating point standard single precision multiplier , 1995, Proceedings of the 12th Symposium on Computer Arithmetic.

[11]  Metin Mete Özbilen,et al.  A SINGLE/DOUBLE PRECISION FLOATING-POINT MULTIPLIER DESIGN FOR MULTIMEDIA APPLICATIONS , 2009 .

[12]  Marimuthu Palaniswami,et al.  A fast-multiplier generator for FPGAs , 1995, Proceedings of the 8th International Conference on VLSI Design.

[13]  Himanshu Thapliyal,et al.  A High Speed Efficient N x N Bit Multiplier Based on Ancient Indian Vedic Mathematics , 2003, VLSI.

[14]  M. Tech,et al.  Design and Implementation of Vedic Multiplier , 2013 .

[15]  Oscal T.-C. Chen,et al.  Low-power multipliers by minimizing switching activities of partial products , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[16]  Jenq-Neng Hwang,et al.  Finite Precision Error Analysis of Neural Network Hardware Implementations , 1993, IEEE Trans. Computers.

[17]  Oscal T.-C. Chen,et al.  Minimization of switching activities of partial products for designing low-power multipliers , 2003, IEEE Trans. Very Large Scale Integr. Syst..