Design optimization of gate-silicided ESD NMOSFETs in a 45nm bulk CMOS technology

Decrease of the drain silicide-blocking-to-gate spacing in gate-silicided-ESD-NMOSFETs improves the TLP and HBM failure levels up to 30%, while no effect is observed when decreasing the source silicide-blocking-to-gate spacing. Failure analysis and simulation results show that current crowding in the drain silicide region accounts for the difference in failure current for the devices.

[1]  S. Selberherr.  Analysis and simulation of semiconductor devices , 1984 .

[2]  J. Holt,et al.  Design of high performance PFETs with strained si channel and laser anneal , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[3]  M. Muhammad,et al.  Evaluation of diode-based and NMOS/Lnpn-based ESD protection strategies in a triple gate oxide thickness 0.13 µm CMOS logic technology , 2001, 2001 Electrical Overstress/Electrostatic Discharge Symposium.

[4]  R. Gauthier,et al.  Analysis of Failure Mechanism on Gate-Silicided and Gate-Non-Silicided, Drain/Source Silicide-blocked ESD NMOSFETs in a 65nm Bulk CMOS Technology , 2006, 2006 13th International Symposium on the Physical and Failure Analysis of Integrated Circuits.

[5]  Mu-Chun Wang,et al.  ESD protection for the tolerant I/O circuits using PESD implantation , 2002 .

[6]  C.C. Russ,et al.  Wafer cost reduction through design of high performance fully silicided ESD devices , 2000, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476).

[7]  Charvaka Duvvury,et al.  Substrate triggering and salicide effects on ESD performance and protection circuit design in deep submicron CMOS processes , 1995, Proceedings of International Electron Devices Meeting.

[8]  J. Sudijono,et al.  Novel Enhanced Stressor with Graded Embedded SiGe Source/Drain for High Performance CMOS Devices , 2006, 2006 International Electron Devices Meeting.

[9]  C. Duvvury,et al.  Substrate pump NMOS for ESD protection applications , 2000, Electrical Overstress/Electrostatic Discharge Symposium Proceedings 2000 (IEEE Cat. No.00TH8476).

[10]  Kai Esmark.  Device simulation of ESD protection elements , 2001 .

[11]  Andreas Daniel Stricker.  Technology computer aided design of ESD protection devices , 2001 .

[12]  Junjun Li,et al.  Analysis of ESD failure mechanism in 65nm bulk CMOS ESD NMOSFETs with ESD implant , 2006, Microelectron. Reliab..

[13]  X. Guggenmos,et al.  Does The Esd-failure Current Obtained By Transmissionline Pulsing Always Correlate To Human Body Model Tests? , 1997, Proceedings Electrical Overstress/Electrostatic Discharge Symposium.

[14]  C. Duvvury,et al.  Dynamic gate coupling of NMOS for efficient output ESD protection , 1992, 30th Annual Proceedings Reliability Physics 1992.

[15]  Mi-Chang Chang,et al.  Circuit and silicide impact on the correlation between TLP and ESD (HBM and MM) , 2004, IEEE International Integrated Reliability Workshop Final Report, 2004.

[16]  Kartikeya Mayaram,et al.  Self-heating effects in basic semiconductor structures , 1993 .