Reconfigurable and adaptive computing

Reconfigurable computing techniques and adaptive systems have attracted great interest as one of the most promising architectures for microprocessors. The origin of reconfigurable systems, programmable logic devices or field programmable gate arrays (FPGAs), has evolved into today’s complex system-on-chip FPGAs, dynamically reconfigurable FPGAs, and furthermore a variety of state-of-the-art adaptive computing devices. Numerous approaches have been conducted to explore more creditable metrics beyond raw performance, such as flexibility, dependability, and low power. This present special issue of International Journal of Electronics aims at introducing and demonstrating the latest research activities on hardware architecture for reconfigurable and adaptive computing systems. The main contribution of each of the included nine papers is briefly introduced in the following. In the paper entitled “On fast iterative mapping algorithms for stripe based coarsegrained reconfigurable architectures”, the authors address the challenge of mapping algorithms on reconfigurable devices with stripe-based coarse-grained reconfigurable architectures by drawing on insights from graph theory. The authors adapt fast, iterative algorithms from hierarchical graph drawing to the problem of mapping to stripe-based architectures. The approach enabled fast design space exploration, rapid performance testing, and flexible programming of this kind of architecture. In the paper entitled “Code mapping algorithm for custom instructions on reconfigurable instruction set processors”, the authors propose a code mapping algorithm, which maps static code of programs to dynamic hot paths as custom instructions. It uses some string matching method. The proposed algorithm can be used as either as fine-grained or coarse-grained mapping. Furthermore, it can find nested matching optimisations within the code. The authors provide a formal proof of correctness together with a time complexity analysis. Moreover, some experimental results are presented. In the paper entitled “CODEM: software/hardware codesign for embedded multicore systems supporting hardware services”, the authors incorporate a novel hot-spot-based profiling technique to observe the hot spot functions while guiding the hardware implementations of the hot spot functions. Furthermore, based on the hot spot of various applications, an adaptive mapping algorithm is presented to partition the application into multiple software/hardware tasks. The authors test the profiling-based design flow with classic sort applications. Experimental results demonstrate that CODEM can efficiently help designers to identify the hot spots. It also outlines a new direction to combine profiling techniques with state-of-the-art reconfigurable computing platforms for specific task acceleration. In the paper entitled “Multiplier-less sharp filter banks using gravitational search algorithm”, the authors detail a multiplier-less nearly perfect reconstruction tree structured non-uniform filter. A meta-heuristic-based algorithm is used and tailored to suit the problem under consideration. Thus, the proposed design results in non-uniform filter banks, which are simple, alias free, linear phase, multiplier-less, and sharp transition International Journal of Electronics, 2015 Vol. 102, No. 1, 1–2, http://dx.doi.org/10.1080/00207217.2014.938315