Constructing IP cores' transparency paths for SoC test access using greedy search

Abstract Today’s SoC design demands efficient test access mechanism to develop and perform manufacturing test. Transparency based methods have their advantages for IP cores’ test reuse in SoC level. In this paper, an IP core transparency paths construction approach employing greedy search strategy based on gate-level heuristic information is proposed. With these transparency paths, IP cores can consecutively transfer one test per clock cycle from their inputs to outputs, and thus can be used in transparency-based test scheme to benefit at-speed testing and decrease the demand of parallel TAMs. The experimental results show lower extra overhead needed in our approach than conventional boundary scan and previous RT level approaches.

[1]  Yervant Zorian,et al.  Test of future system-on-chips , 2000, IEEE/ACM International Conference on Computer Aided Design. ICCAD - 2000. IEEE/ACM Digest of Technical Papers (Cat. No.00CH37140).

[2]  Hideo Fujiwara,et al.  Design for consecutive transparency of cores in system-on-a-chip , 2003, Proceedings. 21st VLSI Test Symposium, 2003..

[3]  Srinivas Raman,et al.  Direct access test scheme-design of block and core cells for embedded ASICs , 1990, Proceedings. International Test Conference 1990.

[4]  Janusz Rajski,et al.  High-frequency, at-speed scan testing , 2003, IEEE Design & Test of Computers.

[5]  Krishnendu Chakrabarty,et al.  Synthesis of transparent circuits for hierarchical and system-on-a-chip test , 2001, VLSI Design 2001. Fourteenth International Conference on VLSI Design.

[6]  Christos A. Papachristou,et al.  Parallelism in structural fault testing of embedded cores , 1998, Proceedings. 16th IEEE VLSI Test Symposium (Cat. No.98TB100231).

[7]  André Ivanov,et al.  Time domain multiplexed TAM: implementation and comparison , 2003, 2003 Design, Automation and Test in Europe Conference and Exhibition.

[8]  M. Marzouki,et al.  CAS-BUS: a scalable and reconfigurable test access mechanism for systems on a chip , 2000, Proceedings Design, Automation and Test in Europe Conference and Exhibition 2000 (Cat. No. PR00537).

[9]  Mounir Benabdenbi,et al.  CAS-BUS: a scalable and reconfigurable test access mechanisms for systems on a chip , 2000, DATE '00.

[10]  Stephen Pateras.  Achieving at-speed structural test , 2003, IEEE Design & Test of Computers.

[11]  Erik Jan Marinissen,et al.  A structured and scalable mechanism for test access to embedded reusable cores , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).

[12]  Shiyuan Yang,et al.  Constructing transparency paths for IP cores using greedy searching strategy , 2004, 13th Asian Test Symposium.

[13]  Nur A. Touba,et al.  Modifying user-defined logic for test access to embedded cores , 1997, Proceedings International Test Conference 1997.

[14]  Sujit Dey,et al.  A fast and low cost testing technique for core-based system-on-chip , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[15]  Lee Whetsel,et al.  An IEEE 1149.1 based test access architecture for ICs with embedded cores , 1997, Proceedings International Test Conference 1997.

[16]  Prab Varma,et al.  A structured test re-use methodology for core-based system chips , 1998, Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270).