NoCTweak: a Highly Parameterizable Simulator for Early Exploration of Performance and Energy of Networks On-Chip

As the number of processing elements (PE) on a single chip increases with each generation of CMOS technology, network on-chip (NoC) has become a de-facto communication fabric for these PEs. Due to high design and test costs for real many-core chips, simulators which allow exploring the best design options for a system before actually building it have been becoming highly necessary in system design and optimization flows. This paper presents NoCTweak, a highly parameterizable NoC simulator used for early exploration of performance and energy efficiency of on-chip networks. The simulator has been developed in SystemC, a C++ plugin, which allows fast modeling of concurrent hardware modules at the cycle-level accuracy. The statistic output results provided by the simulator are the average network latency, throughput, router power and energy per transferred data packet corresponding to a given network configuration, a certain traffic pattern and load. Area, timing and power of router components are post-layout data based on standard-cell libraries.