NoCTweak: a Highly Parameterizable Simulator for Early Exploration of Performance and Energy of Networks On-Chip
暂无分享,去创建一个
[1] Paul V. Gratz,et al. Ocin tsim-DVFS Aware Simulator for NoCs , 2009 .
[2] T.Z. Islam,et al. Gpnocsim - A General Purpose Simulator for Network-On-Chip , 2007, 2007 International Conference on Information and Communication Technology.
[3] Bevan M. Baas,et al. A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network , 2009, 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip.
[4] Niraj K. Jha,et al. GARNET: A detailed on-chip network model inside a full-system simulator , 2009, 2009 IEEE International Symposium on Performance Analysis of Systems and Software.
[5] Bevan M. Baas,et al. DLABS: A dual-lane buffer-sharing router architecture for networks on chip , 2010, 2010 IEEE Workshop On Signal Processing Systems.
[6] Axel Jantsch,et al. NNSE: Nostrum Network-on-Chip Simulation Environment , 2005 .
[7] Boris Grot,et al. Ocin_tsim: a DVFS-aware simulator for NoC based platforms. , 2009 .
[8] Omer Khan,et al. Darsim: A Parallel Cycle-Level NoC Simulator , 2010 .
[9] Valentin Puente,et al. SICOSYS: an integrated framework for studying interconnection network performance in multiprocessor systems , 2002, Proceedings 10th Euromicro Workshop on Parallel, Distributed and Network-based Processing.
[10] Andrew B. Kahng,et al. ORION 2.0: A fast and accurate NoC power and area model for early-stage design space exploration , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.
[11] Anoop Gupta,et al. The SPLASH-2 programs: characterization and methodological considerations , 1995, ISCA.
[12] Kai Li,et al. The PARSEC benchmark suite: Characterization and architectural implications , 2008, 2008 International Conference on Parallel Architectures and Compilation Techniques (PACT).
[13] Bevan M. Baas,et al. RoShaQ: High-performance on-chip router with shared queues , 2011, 2011 IEEE 29th International Conference on Computer Design (ICCD).
[14] Sharad Malik,et al. Orion: a power-performance simulator for interconnection networks , 2002, MICRO.
[15] L. Anghel,et al. A flexible network-on-chip simulator for early design space exploration , 2008, 2008 1st Microsystems and Nanoelectronics Research Conference.
[16] Bevan M. Baas,et al. A Reconfigurable Source-Synchronous On-Chip Network for GALS Many-Core Platforms , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[17] Michael Jones. NoCsim : a versatile network on chip simulator , 2005 .
[18] Bevan M. Baas,et al. A low-cost high-speed source-synchronous interconnection technique for GALS chip multiprocessors , 2009, 2009 IEEE International Symposium on Circuits and Systems.