Module to Perform Multiplication, Division, and Square Root in Systolic Arrays for Matrix Computations

A module that performs multiplication, division, and square root is presented. The implementation is compact because most of the components are shared by all three operations, the complexity being similar to a radix-2 divider. All three operations have the same execution time: one bit of the result is produced per cycle, beginning with the most significant bit. The cycle time is kept small by using redundant addition (carry-save or signed-digit) and a result-digit selection based on a low-precision estimate of the partial remainder. These properties make the module suitable for systolic arrays for matrix computations. Moreover, the communication between these modules in systolic arrays is bit-serial, yet the delay is the same as that for systems with bit-parallel communication

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