Embedded systems: Many cores — Many problems

The embedded-systems industry is about to make a transition to multi-core platforms. This is a highly risky step as several essential problems are not yet solved. In particular, the performance analysis problem has no viable solution for the existing multi-core designs. The main culprit is the interference on shared resources. Several alternative approaches both in architecture and system design and in analysis methods are discussed.

[1]  Petru Eles,et al.  Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip , 2007, RTSS 2007.

[2]  Antti Valmari,et al.  A stubborn attack on state explosion , 1990, Formal Methods Syst. Des..

[3]  R. Wilhelm,et al.  Predictability Considerations in the Design of Multi-Core Embedded Systems ∗ , 2010 .

[4]  Henrik Theiling,et al.  Reliable and Precise WCET Determination for a Real-Life Processor , 2001, EMSOFT.

[5]  Sang Hyuk Son,et al.  Chronos: Feedback Control of a Real Database System Performance , 2007, RTSS 2007.

[6]  Francisco J. Cazorla,et al.  On the evaluation of the impact of shared resources in multithreaded COTS processors in time-critical environments , 2012, TACO.

[7]  Jan Reineke,et al.  Memory Hierarchies, Pipelines, and Buses for Future Architectures in Time-Critical Embedded Systems , 2009, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Bernd Becker,et al.  A Definition and Classification of Timing Anomalies , 2006, WCET.

[9]  Robert P. Dick,et al.  Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis , 2011 .

[10]  Kees G. W. Goossens,et al.  Composable Resource Sharing Based on Latency-Rate Servers , 2009, 2009 12th Euromicro Conference on Digital System Design, Architectures, Methods and Tools.

[11]  Petru Eles,et al.  Bus Access Optimization for Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip , 2007, RTSS.

[12]  Hermann Kopetz,et al.  On the Design of Distributed Time-Triggered Embedded Systems , 2008, J. Comput. Sci. Eng..

[13]  Anthony Rowe,et al.  FireFly Mosaic: A Vision-Enabled Wireless Sensor Networking System , 2007, RTSS 2007.

[14]  Wang Yi,et al.  Cache-aware scheduling and analysis for multicores , 2009, EMSOFT '09.

[15]  Jan Reineke,et al.  Designing Predictable Multicore Architectures for Avionics and Automotive Systems — extended abstract — , 2009 .

[16]  Lothar Thiele,et al.  Worst-case response time analysis of resource access models in multi-core systems , 2010, Design Automation Conference.

[17]  Edward A. Lee,et al.  PRET DRAM controller: Bank privatization for predictability and temporal isolation , 2011, 2011 Proceedings of the Ninth IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS).

[18]  Samarjit Chakraborty,et al.  Proceedings of the seventh ACM international conference on Embedded software , 2009, EMSOFT 2009.

[19]  Marco Caccamo,et al.  Toward the Predictable Integration of Real-Time COTS Based Systems , 2007, 28th IEEE International Real-Time Systems Symposium (RTSS 2007).

[20]  C.B. Watkins,et al.  Transitioning from federated avionics architectures to Integrated Modular Avionics , 2007, 2007 IEEE/AIAA 26th Digital Avionics Systems Conference.

[21]  Lothar Thiele,et al.  Worst case delay analysis for memory interference in multicore systems , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).

[22]  Per Stenström,et al.  Timing anomalies in dynamically scheduled microprocessors , 1999, Proceedings 20th IEEE Real-Time Systems Symposium (Cat. No.99CB37054).

[23]  Michael Paulitsch,et al.  Leveraging Multi-core Computing Architectures in Avionics , 2012, 2012 Ninth European Dependable Computing Conference.

[24]  Sebastian Altmeyer,et al.  Resilience analysis: tightening the CRPD bound for set-associative caches , 2010, LCTES '10.