Clock-powered CMOS: a hybrid adiabatic logic style for energy-efficient computing

Clock-powered logic is a new CMOS logic style which combines adiabatic switching and energy recovery-techniques with conventional CMOS logic styles for the design of low-power computing microsystems. In clock-powered logic high-capacitance nodes are adiabatically switched and powered from AC sources typically the clock lines. Low-capacitance nodes are conventionally switched and powered front a DC supply source. The clocked buffer, a CMOS structure based on bootstrapping, drives the high-capacitance nodes from the clock lines. An analytical model that closely estimates the on-resistance of the bootstrapped nFET is derived. The model is evaluated through H-SPICE simulations. Depending on the CMOS logic style used for the DC-powered blocks, pulse-to-level converters may be required to interface the clocked buffer outputs with the logic blocks. These converters inherently act as low-to-high voltage converters. Therefore, low-power operation can be achieved with clock-powered logic by both increasing the switching time and reducing the voltage swing of clock-powered nodes. This feature of clock-powered logic is evaluated through H-SPICE simulations in which the clocked buffer is compared with conventional supply-scaled CMOS drivers. The clocked buffer combined with adiabatic switching demonstrates superior energy vs. delay scalability than its supply-scaled counterparts.

[1]  Mark Horowitz,et al.  Evaluation of charge recovery circuits and adiabatic switching for low power CMOS design , 1994, Proceedings of 1994 IEEE Symposium on Low Power Electronics.

[2]  Nestoras Tzartzanis,et al.  Energy recovery for low-power CMOS , 1995, Proceedings Sixteenth Conference on Advanced Research in VLSI.

[3]  Kamran Eshraghian,et al.  Principles of CMOS VLSI Design: A Systems Perspective , 1985 .

[4]  William C. Athas,et al.  Energy recovery techniques for cmos microprocessor design , 1998 .

[5]  Hendrikus J. M. Veendrick,et al.  Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits , 1984 .

[6]  J. S. Hall,et al.  An Electroid Switching Model For Reversible Computer Architectures , 1992, Workshop on Physics and Computation.

[7]  Anantha P. Chandrakasan,et al.  Low Power Digital CMOS Design , 1995 .

[8]  Lars Svensson,et al.  A low-power microprocessor based on resonant energy , 1997, IEEE J. Solid State Circuits.

[9]  Nestoras Tzartzanis,et al.  Low-power digital systems based on adiabatic-switching principles , 1994, IEEE Trans. Very Large Scale Integr. Syst..

[10]  N. Tzartzanis,et al.  Clock-powered logic for a 50 MHz low-power RISC datapath , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[11]  Mark Horowitz,et al.  Clustered voltage scaling technique for low-power design , 1995, ISLPED '95.

[12]  Christer Svensson,et al.  High-speed CMOS circuit technique , 1989 .

[13]  Daniel W. Dobberpuhl,et al.  The design and analysis of VLSI circuits , 1985 .

[14]  J. S. Denker,et al.  A review of adiabatic computing , 1994, Proceedings of 1994 IEEE Symposium on Low Power Electronics.

[15]  Thomas F. Knight,et al.  Non-dissipative rail drivers for adiabatic circuits , 1995, Proceedings Sixteenth Conference on Advanced Research in VLSI.

[16]  N. Tzartzanis,et al.  A resonant signal driver for two-phase, almost-non-overlapping clocks , 1996, 1996 IEEE International Symposium on Circuits and Systems. Circuits and Systems Connecting the World. ISCAS 96.