论文信息 - Synthesis Techniques for Masterslice Combinational Logic: A Computer-Aided Evaluation - 字舞流文

Synthesis Techniques for Masterslice Combinational Logic: A Computer-Aided Evaluation

A computer-aided evaluation of certain techniques for combinational-logic synthesis within a masterslice library is presented.

P. N. Bibilo | V. G. Litskevich

[1] Robert K. Brayton,et al. Multilevel logic synthesis , 1990, Proc. IEEE.

[2] Robert K. Brayton,et al. Logic Minimization Algorithms for VLSI Synthesis , 1984, The Kluwer International Series in Engineering and Computer Science.

[3] Giovanni De Micheli,et al. Algorithms for technology mapping based on binary decision diagrams and on Boolean operations , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..