Element integrated dynamic random access memory, and such matrix elements METHOD

An integrated element of dynamic random access memory comprises two cells (C0, C1) for storing respective two bits, a source region (102) and a drain region (103). Each cell comprises a field effect transistor having a gate (4, 14) and an intermediate portion (1, 11). Each transistor further comprises a source (2, 12), a drain (3, 13) and a channel (1c, 11c) respectively arranged in the source region, the drain region and the intermediate portion (1, 11). The element comprises a bias electrode (24) disposed between the intermediate portions (1, 11) of the two transistors, the bias electrode being capacitively coupled with the intermediate portion of each transistor.