Instruction fetch and dispatch scheme with flag‐in‐cache/in‐IBR

[1]  Hirozi Yamada,et al.  A 120-MHz BiCMOS superscalar RISC processor , 1994 .

[2]  Ted G. Lewis.  Living in Real Time, Side A (What Is the Info Age?) , 1995, Computer.

[3]  Gregory F. Grohoski,et al.  Machine Organization of the IBM RISC System/6000 Processor , 1990, IBM J. Res. Dev..

[4]  G. Blanck,et al.  The SuperSPARC microprocessor , 1992, Digest of Papers COMPCON Spring 1992.

[5]  Alan Jay Smith,et al.  Branch Prediction Strategies and Branch Target Buffer Design , 1995, Computer.

[6]  P. Bannon,et al.  A 433 MHz 64 b quad issue RISC microprocessor , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[7]  Yale N. Patt,et al.  Alternative implementations of two-level adaptive branch prediction , 1992, ISCA '92.

[8]  John H. Edmondson,et al.  Superscalar instruction execution in the 21164 Alpha microprocessor , 1995, IEEE Micro.

[9]  Kotaro Shimamura,et al.  A superscalar RISC processor with pseudo vector processing feature , 1995, Proceedings of ICCD '95 International Conference on Computer Design. VLSI in Computers and Processors.

[10]  D. Morris,et al.  Pathlength reduction features in the PA-RISC architecture , 1992, Digest of Papers COMPCON Spring 1992.

[11]  Carlo H. Séquin,et al.  A VLSI RISC , 1982, Computer.