Rate-distortion performance analysis of an analog motion estimation array

Emerging 3D-integration enables integrating high quality image sensors with various massively parallel processing elements. Analog motion estimation is one potential application, which is likely to result in significant benefits in the form of low power or high frame-rate 3D-integrated image sensor-processors. The system-level operation of a proposed analog motion estimation array, enabling all various block sizes from 4×4 to 16×16 is examined. The analog motion estimation circuitry has been designed as a 32×32 test array in 0.13 µm CMOS technology. The transistor-level simulation results combined with H.264/AVC JM 14.2 show equivalent rate-distortion results with SAD as the error measure and an approximately 7% increase in bitrate with a slight increase in image quality for SSE.

[1]  Kari Halonen,et al.  An Analog Processor Array Implementing Interconnect-Efficient Reference Data Shift and SAD/SSD Extraction for Motion Estimation , 2009, EURASIP J. Adv. Signal Process..

[2]  Heung-Kyu Lee,et al.  Block-matching criterion for efficient VLSI implementation of motion estimation , 1996 .

[3]  Douglas Young,et al.  A 4-side tileable back illuminated 3D-integrated Mpixel CMOS image sensor , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[4]  Kari Halonen,et al.  Architecture for Analog Variable Block-Size Motion Estimation , 2007, 2007 IEEE International Conference on Image Processing.