For low power operation in analog CMOS, a lot of attempts using new drain structures to reduce the parasitic capacitance of the source and drain junction capacitance (Cj) have been reported. However, there are not many approaches from the channel doping process. In the usual MOSFET structures, the highly doped channel implanted regions are localized under the gate by the mask used in the channel implantation step in order to reduce Cj. In this process, however, it is limited to localize the channel implanted region by the requirement of the margin for the mask misalignment in the photolithography process. Hence, Cj remained a serious problem to realize the high speed and low power operation. On the other hand, the importance of low frequency noise in RF and microwave circuit applications have been also increased. The authors show the gate length dependence of low frequency noise of MOSFETs. The spectral density of the drain current noise (SID) increases as the gate length decreased. This low frequency noise can be reduced by decreasing the dose of channel implantation process. However it is very difficult to suppress the low frequency noise with optimizing threshold voltage simultaneously. One of the reasons for higher 1/f noise at higher Vth is estimated to be due to the larger damage caused by larger dose of the channel implantation as explained later. The main object of this paper is the investigation of a self-align doped channel (SADC) structure as one of the candidates which can reduce the low frequency noise and the parasitic capacitance simultaneously. In the SADC process, the channel doping process is carried out by using solid phase diffusion from the gate, hence the doped region is fully sell-aligned to the gate, and the junction capacitance can be reduced. Moreover the implantation damage in the channel is reduced. We examine the feasibility study of SADC structure and demonstrate high performance 0.25 /spl mu/m gate length nMOSEFTs with low noise and low power consumption by using SADC structure.