An all-digital data recovery circuit optimization using Matlab/Simulink

The design of an all-digital data recovery (DR) circuit requires careful system-level design space exploration. The advantages of an all-digital implementation are the ease of portability and reduced time-to-market across fabrication processes and with reducing feature sizes. For a selected architecture, this paper explores the effects of sweeping the bit detection interval of a bang-bang phase detector, the phase update interval, and the number of clock phases used for data recovery using a Matlab/Simulink model. The simulation results show the variation of jitter tolerance of the DR circuit with respect to the above parameters. An all-digital architecture can be made adaptive to jitter conditions, if the design trade-offs are known a priori. A statistical graphing/analysis tool is used to present the 3D logarithmic scatter plots.

[1]  B. Razavi,et al.  Analysis and modeling of bang-bang clock and data recovery circuits , 2004, IEEE Journal of Solid-State Circuits.

[2]  T.Y. Yum,et al.  A 50-mW/ch 2.5-gb/s/ch data recovery circuit for the SFI-5 interface with digital eye-tracking , 2004, IEEE Microwave and Wireless Components Letters.

[3]  Moon-Sang Hwang,et al.  A 5 Gb/s 0.25 /spl mu/m CMOS jitter-tolerant variable-interval oversampling clock/data recovery circuit , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[4]  Kaamran Raahemifar,et al.  An overview of design techniques for CMOS phase detectors , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[5]  Chih Yang,et al.  Design of high-speed serial links in CMOS , 1998 .

[6]  Deog-Kyoon Jeong,et al.  Multi-gigabit-rate clock and data recovery based on blind oversampling , 2003, IEEE Commun. Mag..