Semiconductor memory device having function for reducing voltage coupling between bit lines

A semiconductor memory device for reducing bit line voltage coupling is provided to minimize cell data flip phenomenon due to the voltage coupling of bit lines, by minimizing the bit line voltage coupling in a data access operation mode. In a semiconductor memory device, a memory cell array(10) has a plurality of memory cells(1) connected in a matrix of rows and columns between a word line and a bit line pair. A bit line coupling reducing part(42) applies an equalizing release signal to a precharge and equalizer(22) connected to the selected bit line pair when a data access operation mode begins, and then applies equalizing release signals to a precharge and equalizer correspondingly connected to a plurality of unselected bit line pairs. The bit line coupling reducing part is an equalizing driver.