"Burst mode" is a new cipher mode, which is devised dedicatedly for the high performance implementation of Advanced Encryption Standard (AES) and other next generation 128-bit block cipher algorithms. In comparison with the conventional modes, the burst mode achieves a considerable increase in the throughput by employing a novel stream cipher mechanism which can encrypt 64 plaintext blocks through 16 invocations of the block cipher encryption operation. This paper investigates the hardware/software (HW/SW) codesign of the burst mode, to be implemented as an accelerator core running in parallel with a software-based block cipher. Implementation results show that the burst mode with the use of this hardware accelerator raises the speed of the software implementation of AES by four times, achieving the maximum rate of 1.3 Gbps.
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