Discrete wavelet transform architecture using fast processing elements

The paper presents a folded architecture for the Discrete Wavelet Transform using fast processing elements. An improved design method allows the optimization of the register allocation scheme resulting in a reduction of the required hardware.

[1]  I. Daubechies.  Orthonormal bases of compactly supported wavelets , 1988 .

[2]  Stéphane Mallat,et al.  Multifrequency channel decompositions of images and wavelet models , 1989, IEEE Trans. Acoust. Speech Signal Process..

[3]  Mohan Vishwanath.  The recursive pyramid algorithm for the discrete wavelet transform , 1994, IEEE Trans. Signal Process..

[4]  Sethuraman Panchanathan,et al.  VLSI implementation of discrete wavelet transform , 1996, IEEE Trans. Very Large Scale Integr. Syst..

[5]  Martin Vetterli,et al.  Wavelets and filter banks: theory and design , 1992, IEEE Trans. Signal Process..

[6]  T. Nishitani,et al.  VLSI architectures for discrete wavelet transforms , 1993, IEEE Trans. Very Large Scale Integr. Syst..