Layer Router for Grayscale Stego - A Hardware Architecture on FPGA and ASIC Platforms

In the present era of secret communication, steganography has obtained a significant place in information security by means of offering variety of techniques for cleverly hiding the information. In addition to the existing hardware stego algorithms, an adaptive block hardware stego system has been proposed in this paper which follows a shortest path algorithm for performing secret concealment in grayscale images. The proposed image steganographic hardware architecture which adopts traversal procedures predominant in area routing has been implemented bath in Stratix III FPGA as well as ASIC Platforms.

[1]  Lee-Ming Cheng,et al.  Hardware Realization of Steganographic Techniques , 2007 .

[2]  Chin-Feng Lee,et al.  A novel data hiding scheme based on modulus function , 2010, J. Syst. Softw..

[3]  Lee-Ming Cheng,et al.  Hardware Realization of Steganographic Techniques , 2007, Third International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIH-MSP 2007).

[4]  Rengarajan Amirtharajan,et al.  An intelligent chaotic embedding approach to enhance stego-image quality , 2012, Inf. Sci..

[5]  Ahlam Fadhil Mahmood,et al.  An FPGA Implementation of Secured Steganography Communication System , 2014 .

[6]  Kevin Curran,et al.  Digital image steganography: Survey and analysis of current methods , 2010, Signal Process..

[7]  Markus G. Kuhn,et al.  Information hiding-a survey , 1999, Proc. IEEE.

[8]  Magdy Saeb,et al.  Design and implementation of a secret key steganographic micro-architecture employing FPGA , 2004 .

[9]  Claudia Feregrino Uribe,et al.  FPGA Hardware Architecture of the Steganographic ConText Technique , 2008, 18th International Conference on Electronics, Communications and Computers (conielecomp 2008).

[10]  Rengarajan Amirtharaj,et al.  Survey and Analysis of Hardware Cryptographic and Steganographic Systems on FPGA , 2012 .

[11]  B. J. Mohd,et al.  FPGA hardware of the LSB steganography method , 2012, 2012 International Conference on Computer, Information and Telecommunication Systems (CITS).

[12]  Magdy Saeb,et al.  An improved FPGA implementation of the modified hybrid hiding encryption algorithm (MHHEA) for data communication security , 2005, Design, Automation and Test in Europe.

[13]  Rengarajan Amirtharajan,et al.  Stego on FPGA: An IWT Approach , 2014, TheScientificWorldJournal.

[14]  K. Thenmozhi,et al.  Firmware for Data Security: A Review , 2012 .