A 7GS/s, 1.2 V. pseudo logic encoder based flash ADC using TIQ technique

Ultra wide band communication systems extensively rely on low resolution and Giga samples per second data converters. Moreover, technology scaling beyond 90 nm drastically complicates the design of the communication systems. With the increasing complexity in communication systems, greater demand for higher performance and more conversion speed while maintaining power consumption at a reasonable level drives research towards new architectural and topological paradigms. In this paper, a novel architecture implementation for the 4-bit flash ADC is proposed. The design is suitable for low power high-speed applications. The architecture utilizes Threshold Quantization technique (TIQ), the gate sizes are carefully selected so that the input and output rise- and fall-times are about equal. The TIQ technique has been utilized here in order to meet low power requirements and for better implementation in SoC applications. The circuit is designed in CMOS 90 nm technology. A new digital encoder network called the Pseudo- dynamic NMOS encoder is proposed to be used in the proposed TIQ based architecture of flash ADC. The Pseudo-dynamic NMOS encoder outperforms all of the existing encoding networks. The new encoding network offers high data conversion rate with a low power consumption.

[1]  Kaushik Roy,et al.  Low-Power CMOS VLSI Circuit Design , 2000 .

[2]  Chien-In Henry Chen,et al.  Low-Power 4-b 2.5 GSPS Pipelined Flash Analog-to-Digital Converters in 0.13 μm CMOS , 2005, 2005 IEEE Instrumentationand Measurement Technology Conference Proceedings.

[3]  M. S. Bhat,et al.  Design of Resolution Adaptive TIQ Flash ADC using AMS 0.35μm technology , 2008, 2008 International Conference on Electronic Design.

[4]  Yan Wang,et al.  A 42 mW 2 GS/s 4-bit flash ADC in 0.18-μm CMOS , 2009, 2009 International Conference on Wireless Communications & Signal Processing.

[5]  A. Boni,et al.  A novel coding scheme for the ROM of parallel ADCs, featuring reduced conversion noise in the case of single bubbles in the thermometer code , 1998, 1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196).

[6]  Roohie Naaz Mir,et al.  A 4 GS/s, 1.8 V multiplexer encoder based flash ADC using TIQ technique , 2014, 2014 International Conference on Signal Processing and Integrated Networks (SPIN).

[7]  A.H.M. van Roermund,et al.  Smart AD and DA Conversion , 2010 .

[8]  Seung-Hoon Lee,et al.  A 6b 1.2 GS/s 47.8 mW 0.17 mm 2 65 nm CMOS ADC for High-Rate WPAN Systems , 2011 .

[9]  A. Abidi,et al.  A 6 b 1.3 GSample/s A/D converter in 0.35 /spl mu/m CMOS , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[10]  Kyusun Choi,et al.  Design method and automation of comparator generation for flash A/D converter , 2002, Proceedings International Symposium on Quality Electronic Design.

[11]  Dr. P. W. Wani,et al.  Design of a 45 nm TIQ Comparator for High Speed and Low Power 4-Bit Flash ADC , 2010 .

[12]  B. Razavi,et al.  An 8-bit 150-MHz CMOS A/D converter , 1999, IEEE Journal of Solid-State Circuits.

[13]  M. Vertregt,et al.  A 6b 1.6 Gsample/s flash ADC in 0.18 /spl mu/m CMOS using averaging termination , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[14]  Jean-Olivier Plouchart,et al.  An 8-bit 1.5GS/s flash ADC using post-manufacturing statistical selection , 2010, IEEE Custom Integrated Circuits Conference 2010.

[15]  M. S. Sutaone,et al.  A 555/690 MSPS 4-BIT CMOS FLASH ADC USING TIQ COMPARATOR , 2012 .

[16]  P Rajeswari.  An approach to design Flash Analog to Digital Converter for High Speed and Low power Applications , 2012, VLSIC 2012.

[17]  Asad A. Abidi,et al.  A 6 b 1.3 GSample/s A/D converter in 0.35 μm CMOS , 2001 .

[18]  C.-I.H. Chen,et al.  A High Spurious-Free Dynamic Range 4-bit ADC with Nyquist Signal Bandwidth for Wideband Communications , 2007, 2007 IEEE Instrumentation & Measurement Technology Conference IMTC 2007.

[19]  M. Vertregt,et al.  A 6b 1.6 Gsample/s flash ADC in 0.18 μm CMOS using averaging termination , 2002 .

[20]  Liter Siek,et al.  Low-power 4-bit flash ADC for digitally controlled DC-DC converter , 2011, 2011 International Symposium on Integrated Circuits.

[21]  Roohie Naaz Mir,et al.  Design of Low Power High Speed 4-Bit TIQ Based CMOS Flash ADC , 2013 .

[22]  A. Alvandpour,et al.  A 2.5-GS/s 30-mW 4-bit Flash ADC in 90nm CMOS , 2008, 2008 NORCHIP.

[23]  Keshab K. Parhi,et al.  VLSI digital signal processing systems , 1999 .

[24]  Yuh-Shyan Hwang,et al.  New power saving design method for CMOS flash ADC , 2004, The 2004 47th Midwest Symposium on Circuits and Systems, 2004. MWSCAS '04..

[25]  F. Kuttner,et al.  A 6bit, 1.2GSps low-power flash-ADC in 0.13 /spl mu/m digital CMOS , 2004, Design, Automation and Test in Europe.

[26]  Martin Clara,et al.  A 6bit, 1.2GSps Low-Power Flash-ADC in 0.13µm Digital CMOS , 2004, DATE.

[27]  Sreehari Veeramachaneni,et al.  A Novel, Variable Resolution Flash ADC with Sub Flash Architecture , 2010, 2010 IEEE Computer Society Annual Symposium on VLSI.

[28]  Joan Figueras,et al.  On Estimating Leakage Power Consumption for Submicron CMOS Digital Circuits , 2000 .