论文信息 - Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme

Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme

This paper compares areas between a 6T and 8T SRAM cells, in a dual-Vdd scheme and a dynamic voltage scaling (DVS) scheme. In the dual-Vdd scheme, we predict that the area of the 6T cell keep smaller than that of the 8T cell, over feature technology nodes all down to 32 nm. In contrast, in the DVS scheme, the 8T cell will becomes superior to the 6T cell after the 32-nm node, in terms of the area.

[1] Masahiko Yoshimoto,et al. Area Optimization in 6T and 8T SRAM Cells Considering Vth Variation in Future Processes , 2007, IEICE Trans. Electron..

[2] Masahiro Nomura,et al. A read-static-noise-margin-free SRAM cell for low-VDD and high-speed applications , 2006, IEEE Journal of Solid-State Circuits.

[3] H. Fujiwara,et al. An Area-Conscious Low-Voltage-Oriented 8T-SRAM Design under DVS Environment , 2007, 2007 IEEE Symposium on VLSI Circuits.

[4] K. Nii,et al. 90-nm process-variation adaptive embedded SRAM modules with power-line-floating write technique , 2006, IEEE Journal of Solid-State Circuits.

[5] Masahiko Yoshimoto,et al. A 0.3-V Operating, Vth-Variation-Tolerant SRAM under DVS Environment for Memory-Rich SoC in 90-nm Technology Era and Beyond , 2006, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[6] P. Stolk,et al. Modeling statistical dopant fluctuations in MOS transistors , 1998 .

[7] K. Takeda,et al. A read-static-noise-margin-free SRAM cell for low-V/sub dd/ and high-speed applications , 2005, ISSCC. 2005 IEEE International Digest of Technical Papers. Solid-State Circuits Conference, 2005..

[8] Takakuni Douseki,et al. Static‐noise margin analysis for a scaled‐down CMOS memory cell , 1992 .