Blade - A Timing Violation Resilient Asynchronous Design Template
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[1] Aditya Jagirdar,et al. Efficient Flip-Flop Designs for SET / SEU Mitigation with Tolerance to Crosstalk Induced Signal Delays , 2007 .
[2] Jian Liu,et al. Soft MOUSETRAP: A Bundled-Data Asynchronous Pipeline Scheme Tolerant to Random Variations at Ultra-Low Supply Voltages , 2013, 2013 IEEE 19th International Symposium on Asynchronous Circuits and Systems.
[3] Luciano Lavagno,et al. Methodology and tools for state encoding in asynchronous circuit synthesis , 1996, DAC '96.
[4] F. Ashcroft,et al. VIII. References , 1955 .
[5] Luciano Lavagno,et al. Desynchronization: Synthesis of Asynchronous Circuits From Synchronous Specifications , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[6] Sunil P. Khatri,et al. A PLA based asynchronous micropipelining approach for subthreshold circuit design , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[7] J. Draper,et al. The DF-dice storage element for immunity to soft errors , 2005, 48th Midwest Symposium on Circuits and Systems, 2005..
[8] David Blaauw,et al. Bubble Razor: Eliminating Timing Margins in an ARM Cortex-M3 Processor in 45 nm CMOS Using Architecturally Independent Error Detection and Correction , 2013, IEEE Journal of Solid-State Circuits.
[9] Eckhard Grass,et al. BIST technique for GALS systems , 2005, 8th Euromicro Conference on Digital System Design (DSD'05).
[10] Kenneth Y. Yun,et al. Automatic synthesis of extended burst-mode circuits. II. (Automaticsynthesis) , 1999, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[11] Jan M. Rabaey,et al. Statistical Analysis and Optimization of Asynchronous Digital Circuits , 2012, 2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems.
[12] S. Schwartz,et al. On the distribution function and moments of power sums with log-normal components , 1982, The Bell System Technical Journal.
[13] Teresa H. Y. Meng,et al. Covering conditions and algorithms for the synthesis of speed-independent circuits , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[14] B.I. Dervisoglu,et al. DESIGN FOR TESTABILITY USING SCANPATH TECHNIQUES FOR PATH-DELAY TEST AND MEASUREMENT , 1991, 1991, Proceedings. International Test Conference.
[15] Yusuf Leblebici,et al. Current sensing completion detection for subthreshold asynchronous circuits , 2007, 2007 18th European Conference on Circuit Theory and Design.
[16] Kwen-Siong Chong,et al. An ultra-low power asynchronous quasi-delay-insensitive (QDI) sub-threshold memory with bit-interleaving and completion detection , 2010, Proceedings of the 8th IEEE International NEWCAS Conference 2010.
[17] David Blaauw,et al. Analysis and mitigation of variability in subthreshold design , 2005, ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005..
[18] Thomas J. Chaney,et al. Q-Modules: Internally Clocked Delay-Insensitive Modules , 1988, IEEE Trans. Computers.
[19] Melvin A. Breuer,et al. Digital systems testing and testable design , 1990 .
[20] Robert C. Aitken,et al. TIMBER: Time borrowing and error relaying for online timing error resilience , 2010, 2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010).
[21] Andrew K. Martin,et al. A Self-Correcting Soft Error Tolerant Flop-Flop , 2005 .
[22] David Blaauw,et al. Razor II: In Situ Error Detection and Correction for PVT and SER Tolerance , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[23] Ivan E. Sutherland,et al. Micropipelines , 1989, Commun. ACM.
[24] D. Dill,et al. Automatic Synthesis of Extended Burst-Mode Circuits : Part II ( Automatic Synthesis ) , 1996 .
[25] Steven M. Nowick,et al. MOUSETRAP: ultra-high-speed transition-signaling asynchronous pipelines , 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.
[26] Stephen B. Furber,et al. Built-in self-testing of micropipelines , 1997, Proceedings Third International Symposium on Advanced Research in Asynchronous Circuits and Systems.
[27] Peter A. Beerel,et al. A Designer's Guide to Asynchronous VLSI: Micropipeline design , 2010 .
[28] Toshinori Sato,et al. A Simple Flip-Flop Circuit for Typical-Case Designs for DFM , 2007, 8th International Symposium on Quality Electronic Design (ISQED'07).
[29] Kaushik Roy,et al. Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation , 2010, IEEE Journal of Solid-State Circuits.
[30] David Blaauw,et al. Bubble Razor: An architecture-independent approach to timing-error detection and correction , 2012, 2012 IEEE International Solid-State Circuits Conference.
[31] Peter A. Beerel,et al. A Designer's Guide to Asynchronous VLSI , 2010 .
[32] Trevor Mudge,et al. Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..
[33] Peter A. Beerel,et al. Stochastic analysis of Bubble Razor , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).
[34] Niraj K. Jha,et al. MINIMALIST: An Environment for the Synthesis, Verification and Testability of Burst-Mode Asynchronous Machines , 1999 .
[35] Jan M. Rabaey,et al. Asynchronous Computing in Sense Amplifier-Based Pass Transistor Logic , 2009, 2008 14th IEEE International Symposium on Asynchronous Circuits and Systems.
[36] K.A. Bowman,et al. Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance , 2009, IEEE Journal of Solid-State Circuits.
[37] Anantha Chandrakasan,et al. Variation-Driven Device Sizing for Minimum Energy Sub-threshold Circuits , 2006, ISLPED'06 Proceedings of the 2006 International Symposium on Low Power Electronics and Design.
[38] Dennis Sylvester,et al. Razor-lite: A side-channel error-detection register for timing-margin recovery in 45nm SOI CMOS , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.
[39] M. S.. Design of a low-latency asynchronous adder using speculative completion , 2004 .
[40] David M. Bull,et al. RazorII: In Situ Error Detection and Correction for PVT and SER Tolerance , 2009, IEEE Journal of Solid-State Circuits.