Chapter 9 – Conclusion

Publisher Summary This concluding chapter sums up the formal analysis and verification techniques for high-level design descriptions presented throughout the book. It also discusses the future prospects for these techniques. The static analysis methods can detect various kinds of design inappropriateness without fully traversing the design descriptions and can be applied to large designs. Model-checking algorithms for high-level design descriptions have been presented. The synchronization verification methods can be combined with equivalence-checking methods so that equivalence among concurrent processes can be formally reasoned about. Also, semi-formal verification technology has been introduced. These methods fall in between simulations and formal verification, and they can be applied to larger design descriptions even when their complexity would overwhelm formal analysis. There is much room for future research, as high-level design support has just begun. Boolean reasoning methods are improving, especially the performance of satisfiability (SAT) solvers. The SAT-based model checking and equivalence checking for logic design levels, such as register transfer level (RTL), are becoming very practical. Other formal verification techniques are still undergoing intensive research. It is strongly believed that the high-level design process can become much more efficient with formal verification technology.