Multicore-Aware Code Positioning to Improve Worst-Case Performance

Inter-thread interferences in shared caches can significantly affect the worst-case execution time (WCET) of real-time tasks running on multi-core chips. In this paper, we study three multicore-aware code positioning methods to reduce the inter-core L2 cache interferences between co-running real-time threads. One strategy focuses on decreasing the longest WCET among the co-running threads, and two other methods aim at achieving fairness in terms of the amount or percentage of WCET reduction among co-running threads. Our experiments indicate that the proposed multicore-aware code positioning approaches not only improve the worst-case performance of the real-time threads, but also make tradeoffs between efficiency and fairness for threads running on multi-core platforms.

[1]  Frank Mueller,et al.  Compiler support for software-based cache partitioning , 1995, Workshop on Languages, Compilers, & Tools for Real-Time Systems.

[2]  Sharad Malik,et al.  Performance Analysis of Embedded Software Using Implicit Path Enumeration , 1995, 32nd Design Automation Conference.

[3]  James H. Anderson,et al.  Soft Real-Time Scheduling on Performance Asymmetric Multicore Platforms , 2007, 13th IEEE Real Time and Embedded Technology and Applications Symposium (RTAS'07).

[4]  W. W. Hwu,et al.  Achieving high instruction cache performance with an optimizing compiler , 1989, ISCA '89.

[5]  Dirk Grunwald,et al.  Reducing branch costs via branch alignment , 1994, ASPLOS VI.

[6]  Sharad Malik,et al.  Cache modeling and path analysis for real-time software , 1996 .

[7]  Scott McFarling,et al.  Program optimization for instruction caches , 1989, ASPLOS III.

[8]  Henrik Theiling,et al.  Reliable and Precise WCET Determination for a Real-Life Processor , 2001, EMSOFT.

[9]  Microsystems Sun,et al.  Jini^ Architecture Specification Version 2.0 , 2003 .

[10]  Per Stenström,et al.  Timing anomalies in dynamically scheduled microprocessors , 1999, Proceedings 20th IEEE Real-Time Systems Symposium (Cat. No.99CB37054).

[11]  Wei Zhang,et al.  WCET Analysis for Multi-Core Processors with Shared L2 Instruction Caches , 2008, 2008 IEEE Real-Time and Embedded Technology and Applications Symposium.

[12]  B. R. Rau,et al.  HPL-PD Architecture Specification:Version 1.1 , 2000 .

[13]  Andrew Wolfe,et al.  Software-based cache partitioning for real-time applications , 1994 .

[14]  Karl Pettis,et al.  Profile guided code positioning , 1990, PLDI '90.

[15]  Jay K. Strosnider,et al.  SMART (strategic memory allocation for real-time) cache design using the MIPS R3000 , 1990, [1990] Proceedings 11th Real-Time Systems Symposium.

[16]  David R. Karger,et al.  Near-optimal intraprocedural branch alignment , 1997, PLDI '97.

[17]  D. B. Kirk,et al.  SMART (strategic memory allocation for real-time) cache design , 1989, [1989] Proceedings. Real-Time Systems Symposium.

[18]  Chanik Park,et al.  Real-time scheduling in heterogeneous dual-core architectures , 2006, 12th International Conference on Parallel and Distributed Systems - (ICPADS'06).

[19]  David B. Whalley,et al.  ParaScale: exploiting parametric timing analysis for real-time schedulers and dynamic voltage scaling , 2005, 26th IEEE International Real-Time Systems Symposium (RTSS'05).

[20]  James H. Anderson,et al.  A Hybrid Real-Time Scheduling Approach for Large-Scale Multicore Platforms , 2007, 19th Euromicro Conference on Real-Time Systems (ECRTS'07).

[21]  David B. Whalley,et al.  Timing analysis for data caches and set-associative caches , 1997, Proceedings Third IEEE Real-Time Technology and Applications Symposium.

[22]  David B. Kirk,et al.  Process dependent static cache partitioning for real-time systems , 1988, Proceedings. Real-Time Systems Symposium.

[23]  David B. Whalley,et al.  Bounding Pipeline and Instruction Cache Performance , 1999, IEEE Trans. Computers.

[24]  Raimund Kirner,et al.  Automatic timing model generation by CFG partitioning and model checking , 2005, Design, Automation and Test in Europe.

[25]  Paul Lokuciejewski,et al.  WCET-driven Cache-based Procedure Positioning Optimizations , 2008, 2008 Euromicro Conference on Real-Time Systems.

[26]  Jakob Engblom,et al.  The worst-case execution-time problem—overview of methods and survey of tools , 2008, TECS.

[27]  James H. Anderson,et al.  Real-Time Scheduling on Multicore Platforms , 2006, 12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS'06).

[28]  Reinhard Wilhelm,et al.  Efficient and Precise Cache Behavior Prediction for Real-Time Systems , 1999, Real-Time Systems.

[29]  David B. Whalley,et al.  WCET code positioning , 2004, 25th IEEE International Real-Time Systems Symposium.