Acoustic micro imaging of flip chip interconnects

Abstract Using a flip chip configuration to interconnect a die with its substrate gives the device a smaller footprint (very desirable in multi-chip modules) and avoids the register and planarity problems one would face with lead bonding, such as TAB interconnects. The drawback is that flip chips have very small and very critical internal bonds which must be inspected to ensure the reliability of the device. Visual inspection methods, which are the most widely used methods for the inspection of interconnect quality, are not adequate for the evaluation of flip chip attach. The solder joints are located below the die and the bonds are often located throughout the face of the chip, not just at the perimeter of the die. This renders them uinspectable by visual techniques.