A Challenge for an Efficient AMI-based Cache System on FPGA Soft Processors

FPGA soft processors are widely used for embedded applications because of their versatility. High performance cache with fewer resources for FPGA soft processors has become an important issue. Conventional approaches to improve cache performance are following: larger cache capacity, larger associativity and proper line size. These approaches work effectively in many cases, however, cache conflicts occur frequently in some applications because the best cache configuration depends on application characteristics. We propose a cache system on FPGA soft processors which selects the suitable number of cache lines depending on an application to be run. Our proposed system uses Arbitrary Modulus Indexing (AMI) to implement non-power-of-2 cache lines. We evaluate how AMI affects the performance of our proposed system. In evaluation, we confirmed that our proposed cache system can achieve 8.0 speedup on average against conventional cache systems.

[1]  François Bodin,et al.  Skewed Associativity Improves Program Performance and Enhances Predictability , 1997, IEEE Trans. Computers.

[2]  Alvin M. Despain,et al.  A study of cache hashing functions for symbolic applications in micro-parallel processors , 1994, Proceedings of 1994 International Conference on Parallel and Distributed Systems.

[3]  Trevor Mudge,et al.  MiBench: A free, commercially representative embedded benchmark suite , 2001 .

[4]  André Seznec,et al.  A case for two-way skewed-associative caches , 1993, ISCA '93.

[5]  Christoforos E. Kozyrakis,et al.  The ZCache: Decoupling Ways and Associativity , 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.

[6]  Jaejin Lee,et al.  Eliminating conflict misses using prime number-based cache indexing , 2005, IEEE Transactions on Computers.

[7]  Jeffrey R. Diamond,et al.  Arbitrary Modulus Indexing , 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.

[8]  Tony Givargis Improved indexing for cache miss reduction in embedded systems , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).