FPGA implementations for parallel multidimensional filtering algorithms
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[1] A. Prasad Vinod,et al. New Reconfigurable Architectures for Implementing FIR Filters With Low Complexity , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[2] Stanley R. Sternberg. Parallel architectures for image processing , 1979, COMPSAC.
[3] Said Boussakta,et al. Signal analysis of medical acoustic sounds with applications to chest medicine , 2007, J. Frankl. Inst..
[4] R. DeCharms. Applications of real-time fMRI , 2008, Nature Reviews Neuroscience.
[5] Fang Hao,et al. IPv6 Lookups using Distributed and Load Balanced Bloom Filters for 100Gbps Core Router Line Cards , 2009, IEEE INFOCOM 2009.
[6] Donald G. Bailey,et al. Development Issues in Using FPGAs for Image Processing , 2007 .
[7] C. Burrus,et al. Fast one-dimensional digital convolution by multidimensional techniques , 1974 .
[8] Ye Min. FPGA Based Real-Time Image Filtering and Edge Detection , 2007 .
[9] Steven Trimberger,et al. A 90-nm Low-Power FPGA for Battery-Powered Applications , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[10] Hugo R. Shi,et al. Toeplitz-based iterative image reconstruction for MRI with correction for magnetic field inhomogeneity , 2005, IEEE Transactions on Signal Processing.
[11] A. Kübler,et al. Training locked-in patients: a challenge for the use of brain-computer interfaces , 2003, IEEE Transactions on Neural Systems and Rehabilitation Engineering.
[12] R. Fontaine,et al. Real Time Implementation of a Wiener Filter Based Crystal Identification Algorithm , 2008, IEEE Transactions on Nuclear Science.
[13] Alexandre Yakovlev,et al. Improved parameterized efficient FPGA implementations of parallel 1-D filtering algorithms using Xilinx System Generator , 2010, The 10th IEEE International Symposium on Signal Processing and Information Technology.
[14] Fan Yang,et al. Fast and Robust Face Detection on a Parallel Optimized Architecture Implemented on FPGA , 2009, IEEE Transactions on Circuits and Systems for Video Technology.
[15] Said Boussakta,et al. Efficient 3-D parallel FIR filtering algorithm , 2007, 2007 15th European Signal Processing Conference.
[16] Quang Nguyen,et al. The parallelization of video processing , 2009, IEEE Signal Processing Magazine.
[17] D. A. Yuen,et al. Parallel interactive visualization of 3D mantle convection , 1996 .
[18] Hari C. Reddy,et al. Design of multidimensional FIR digital filters using the symmetrical decomposition technique , 1994, IEEE Trans. Signal Process..
[19] Sander Stuijk,et al. Throughput Analysis of Synchronous Data Flow Graphs , 2006, Sixth International Conference on Application of Concurrency to System Design (ACSD'06).
[20] Desmond C. McLernon,et al. Parallelisation of the 1-D block filter algorithm to run on multiple DSPs , 2002, 9th International Conference on Electronics, Circuits and Systems.
[21] Swapna Banerjee,et al. A memory efficient 3-D DWT architecture , 2003, 16th International Conference on VLSI Design, 2003. Proceedings..
[22] Mile K. Stojcev. Algorithms sequential and parallel: a unified approach , 2001 .
[23] Brian D. Rigling,et al. Autocorrelation Constraints in Radar Waveform Optimization for Detection , 2012, IEEE Transactions on Aerospace and Electronic Systems.
[24] Thippur V. Sreenivas,et al. Linear filtering in DCT IV/DST IV and MDCT/MDST domain , 2009, Signal Process..
[25] Sao-Jie Chen,et al. Real-time implementation of noise-immune gradient-based edge detection , 2005, International Symposium on Signals, Circuits and Systems, 2005. ISSCS 2005..
[26] Vicente Alarcón Aquino,et al. Design and implementation of the discrete wavelet transform on an FPGA platform to process data sets of up to three dimensions , 2012, CONIELECOMP 2012, 22nd International Conference on Electrical Communications and Computers.
[27] L. Litwin. FIR and IIR digital filters , 2000 .
[28] Joachim Hornegger,et al. Evaluation of state-of-the-art hardware architectures for fast cone-beam CT reconstruction , 2011, Parallel Comput..
[29] Guillermo Garcia. Optimal Filter Partition for Efficient Convolution with Short Input/Output Delay , 2002 .
[30] Qing Huo Liu,et al. An Efficient MR Image Reconstruction Method for Arbitrary K-space Trajectories Without Density Compensation , 2006, 2006 International Conference of the IEEE Engineering in Medicine and Biology Society.
[31] Mohamed B. Abdelhalim,et al. Implementation of 3D-DCT based video encoder/decoder system , 2003, Signals, Circuits and Systems, 2003. SCS 2003. International Symposium on.
[32] Sunanda Mitra,et al. A fast algorithm for registration of individual frames and information recovery in fluorescein angiography video image analysis , 2002, Proceedings Fifth IEEE Southwest Symposium on Image Analysis and Interpretation.
[33] Martin C. Herbordt,et al. Achieving High Performance with FPGA-Based Computing , 2007, Computer.
[34] Gao Meiguo,et al. Design of Real-time Convolution Processor and its Application in Radar Echo Signal Simulator , 2008, 2008 International Conference on Computer Science and Information Technology.
[35] Akihiko Konagaya,et al. Multidimensional dynamic programming for homology search , 2005, International Conference on Field Programmable Logic and Applications, 2005..
[36] Victor M. Brea,et al. FPGA-accelerated retinal vessel-tree extraction , 2009, 2009 International Conference on Field Programmable Logic and Applications.
[37] Carlos H. Llanos,et al. An unified approach for convolution-based image filtering on reconfigurable systems , 2011, 2011 VII Southern Conference on Programmable Logic (SPL).
[38] Jie Xiang,et al. The study of data analysis methods based on FMRI brain-computer interface , 2010, 2010 IEEE Fifth International Conference on Bio-Inspired Computing: Theories and Applications (BIC-TA).
[39] Said Boussakta,et al. Parameterized FPGA-based architecture for parallel 1-D filtering algorithms , 2011, International Workshop on Systems, Signal Processing and their Applications, WOSSPA.
[40] Mike Darnell,et al. A New Architecture For Radix-2 New Mersenne Number Transform , 2006, 2006 IEEE International Conference on Communications.
[41] Abbes Amira,et al. Medical image denoising on field programmable gate array using finite Radon transform , 2012, IET Signal Process..
[42] Shahid Masud,et al. Teaching and research in FPGA based Digital Signal Processing using Xilinx System Generator , 2012, 2012 IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP).
[43] John Y. Cheung,et al. Design of Low Memory Usage Discrete Wavelet Transform on FPGA Using Novel Diagonal Scan , 2006, International Symposium on Parallel Computing in Electrical Engineering (PARELEC'06).
[44] Lei Ye,et al. A Reconfigurable Parallel Architecture for Image Computing , 2006, 2006 6th World Congress on Intelligent Control and Automation.
[45] Osama A. Elsayed. Optimized algorithms for real time medical image registration , 2010, 4th European Education and Research Conference (EDERC 2010).
[46] Du Jiaxi,et al. Inspection and Orientation Model of Digital Camera , 2009, 2009 Second International Conference on Information and Computing Science.
[47] W. Manning,et al. Myocardial elastography - comparison to results using MR cardiac tagging , 2003, IEEE Symposium on Ultrasonics, 2003.
[48] Ian Grout,et al. Digital Systems Design with FPGAs and CPLDs , 2008 .
[49] N. Birbaumer,et al. fMRI Brain-Computer Interfaces , 2008, IEEE Signal Processing Magazine.
[50] Alexandre Yakovlev,et al. Performance efficient FPGA implementation of parallel 2-D MRI image filtering algorithms using Xilinx system generator , 2010, 2010 7th International Symposium on Communication Systems, Networks & Digital Signal Processing (CSNDSP 2010).
[51] Clive ldMax rd Maxfield,et al. The design warrior's guide to FPGAs , 2004 .
[52] Patrick Longa,et al. A Flexible Design of Filterbank Architectures for Discrete Wavelet Transforms , 2007, 2007 IEEE International Conference on Acoustics, Speech and Signal Processing - ICASSP '07.
[53] James Hwang,et al. Building Custom FIR Filters Using System Generator , 2002, FPL.
[54] Desmond C. McLernon,et al. High performance 2D parallel block-filtering system for real-time imaging applications using the Sharc ADSP21060 , 2003, Real Time Imaging.
[55] Jeffrey A. Fessler,et al. Model-Based Image Reconstruction for MRI , 2010, IEEE Signal Processing Magazine.
[56] Nabeel Shirazi,et al. System Level Tools for DSP in FPGAs , 2001, FPL.
[57] Boonwat Attachoo,et al. A new approach for colored satellite image enhancement , 2009, 2008 IEEE International Conference on Robotics and Biomimetics.
[58] Said Boussakta. A novel method for parallel image processing applications , 1999, J. Syst. Archit..
[59] Abdellatif Mtibaa,et al. Real Time Implementation of Detection of Bacteria in Microscopic Images Using System Generator , 2012 .
[60] Klaus Mueller,et al. Efficiently GPU-accelerating long kernel convolutions in 3-D DIRECT TOF PET reconstruction via a kernel decomposition scheme , 2010, IEEE Nuclear Science Symposuim & Medical Imaging Conference.
[61] Srihari Cadambi,et al. A Massively Parallel Coprocessor for Convolutional Neural Networks , 2009, 2009 20th IEEE International Conference on Application-specific Systems, Architectures and Processors.
[62] Anil K. Jain,et al. Convolution on Splash 2 , 1995, Proceedings IEEE Symposium on FPGAs for Custom Computing Machines.
[63] T. Mahalakshmi,et al. Vlsi Implementation of Edge Detection for Images , 2012 .
[64] Tian-Bo Deng,et al. Decomposition-based design of linear phase 3-D digital filters , 1996, Signal Process..
[65] J. C. Moctezuma,et al. Architecture for filtering images using Xilinx system generator , 2008 .
[66] De Xu,et al. A vision system with multiple cameras designed for humanoid robots to play table tennis , 2011, 2011 IEEE International Conference on Automation Science and Engineering.
[67] Michel Wedel,et al. Challenges and opportunities in high-dimensional choice data analyses , 2008 .
[68] Vinay Singh,et al. Accelerating bit error rate testing using a system level design tool , 2003, 11th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2003. FCCM 2003..
[69] Narayanan Vijaykrishnan,et al. A reconfigurable platform for the design and verification of domain-specific accelerators , 2012, 17th Asia and South Pacific Design Automation Conference.
[70] Desmond C. McLernon,et al. The implementation of a new 3-D parallel filtering algorithm on the SHARC ADSP21060 platform , 2003 .
[72] Sheng-zhen Jin,et al. The Implement of High Speed Correlation Tracking Algorithm Based on FPGA in Space Solar Telescope , 2006, 2006 8th international Conference on Signal Processing.
[73] Alvy Ray Smith,et al. 3-D transformations of images in scanline order , 1980, SIGGRAPH '80.
[74] Josef Goette,et al. Comparing Signal Processing Hardware-Synthesis Methods Based on the Matlab Tool-Chain , 2011, 2011 Sixth IEEE International Symposium on Electronic Design, Test and Application.
[75] Mohd Fauzi Bin Othman,et al. An overview of MRI brain classification using FPGA implementation , 2010, 2010 IEEE Symposium on Industrial Electronics and Applications (ISIEA).
[76] Fan Yang,et al. A Parallel Face Detection System Implemented on FPGA , 2007, 2007 IEEE International Symposium on Circuits and Systems.
[77] Kihong Shin,et al. Fundamentals of Signal Processing for Sound and Vibration Engineers , 2008 .
[78] Desmond C. McLernon,et al. Three-dimensional digital filtering algorithm for parallel DSP implementation , 2003, Proceedings 2003 International Conference on Image Processing (Cat. No.03CH37429).
[79] J. Bernhard,et al. Model Based Development of the Digital Part of a RFID Transponder with Xilinx System Generator for a FPGA Platform , 2012, 2012 Fourth International EURASIP Workshop on RFID Technology.
[80] Said Boussakta,et al. Pipeline Architectures for Radix-2 New Mersenne Number Transform , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.
[81] Michael J. Flynn,et al. Parallel architectures , 1996, CSUR.
[82] J.R. Mohammed,et al. Real-Time Implementation of New Adaptive Beamformer Sensor Array For Speech Enhancement in Hearing Aid , 2007, 2007 3rd International Conference on Intelligent Sensors, Sensor Networks and Information.
[83] William G. Gardner,et al. Efficient Convolution without Input/Output Delay , 1995 .
[84] C. T. Johnston. Implementing Image Processing Algorithms on FPGAs , 2005 .
[85] Arjuna Madanayake,et al. VLSI Architectures for the 4-Tap and 6-Tap 2-D Daubechies Wavelet Filters Using Algebraic Integers , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.
[86] Abbes Amira,et al. A reconfigurable coprocessor for high-resolution image filtering in real time , 2003, 10th IEEE International Conference on Electronics, Circuits and Systems, 2003. ICECS 2003. Proceedings of the 2003.
[87] Jacir Luiz Bordim,et al. An Energy-Optimum and Communication-Time Efficient Protocol for Allocation, Scheduling and Routing in Wireless Networks , 2012, 2012 IEEE 26th International Parallel and Distributed Processing Symposium Workshops & PhD Forum.
[88] K. SivaNagi Reddy,et al. Noval approach image processing algorithms on hardware implementation for surveillance systems , 2011 .
[89] J. Gallant,et al. Identifying natural images from human brain activity , 2008, Nature.
[90] Hui Zhang,et al. A Reconfigurable System-on-chip Architecture for Medical Imaging: Preliminary Results , 2005, 2005 IEEE Engineering in Medicine and Biology 27th Annual Conference.
[91] V. O. Roda,et al. Image convolution processing: A GPU versus FPGA comparison , 2012, 2012 VIII Southern Conference on Programmable Logic.
[92] Alexandre Yakovlev. Energy-modulated computing , 2011, 2011 Design, Automation & Test in Europe.
[93] Said Boussakta,et al. FPGA-Based Architecture for a Generalized Parallel 2-D MRI Filtering Algorithm , 2012 .
[94] N. Alberto Borghese,et al. A portable modular system for automatic acquisition of 3D objects , 2000, IEEE Trans. Instrum. Meas..
[95] Ana Toledo Moreo,et al. Experiences on developing computer vision hardware algorithms using Xilinx system generator , 2005, Microprocess. Microsystems.
[96] S. Sankaraiah,et al. Implementation of mobile platform using Qt and OpenCV for image processing applications , 2011, 2011 IEEE Conference on Open Systems.
[97] Zahid Hussain. Digital image processing - practical applications of parallel processing techniques , 1991, Ellis Horwood series in digital and signal processing.
[98] Kaushik Roy,et al. Low-Power Digital Signal Processing Using Approximate Adders , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[99] Abbes Amira,et al. FPGA implementations of fast fourier transforms for real-time signal and image processing , 2003, Proceedings. 2003 IEEE International Conference on Field-Programmable Technology (FPT) (IEEE Cat. No.03EX798).
[100] G. Goavec-Merou,et al. FPGA Implementation of Diffusive Realization for a Distributed Control Operator , 2010, 2010 First Workshop on Hardware and Software Implementation and Control of Distributed MEMS.
[101] Nanning Zheng,et al. Low-power and high-speed VLSI architecture for lifting-based forward and inverse wavelet transform , 2005, IEEE Transactions on Consumer Electronics.
[102] Sao-Jie Chen,et al. Real-time realisation of noise-immune gradient-based edge detector , 2006 .
[103] Desmond C. McLernon,et al. A high performance 3-D parallel filtering algorithm using the vector radix fast Hartley transform , 2003, Proceedings of the Fourth International Conference on Parallel and Distributed Computing, Applications and Technologies.
[104] J.Y. Fourniols,et al. A 3D real-time vision system based on passive stereovision algorithms: Application to laparoscopic surgical manipulations , 2006, 2006 2nd International Conference on Information & Communication Technologies.
[105] Xinghai Li,et al. Block size considerations for multidimensional convolution and correlation , 1992, IEEE Trans. Signal Process..
[106] Yasuhiro Kobayashi,et al. Optimal Periodic Memory Allocation for Image Processing With Multiple Windows , 2009, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.
[107] Patrick Degenaar,et al. Parallelism to reduce power consumption on FPGA spatiotemporal image processing , 2008, 2008 IEEE International Symposium on Circuits and Systems.
[108] Anil K. Jain,et al. An Efficient Two-Dimensional FFT Algorithm , 1981, IEEE Transactions on Pattern Analysis and Machine Intelligence.
[109] Nicolai Petkov,et al. Edge and line oriented contour detection: State of the art , 2011, Image Vis. Comput..
[110] Edwin Hsing-Mean Sha,et al. Fully Parallel Hardware/Software Codesign for Multi-Dimensional DSP Applications , 1996, CODES.
[111] V. Elamaran,et al. FPGA IMPLEMENTATION OF POINT PROCESSES USING XILINX SYSTEM GENERATOR , 2012 .
[112] María José Moure,et al. Features, Design Tools, and Application Domains of FPGAs , 2007, IEEE Transactions on Industrial Electronics.
[113] David C. C. Wang,et al. Digital image enhancement: A survey , 1983, Comput. Vis. Graph. Image Process..
[114] D. Y. von Cramon,et al. Comparison of Filtering Methods for fMRI Datasets , 1999, NeuroImage.
[115] Peshala V. Pahalawatta,et al. A subjective comparison of depth image based rendering and frame compatible stereo for low bit rate 3D video coding , 2012, Proceedings of The 2012 Asia Pacific Signal and Information Processing Association Annual Summit and Conference.
[116] John Williams,et al. Reconfigurable FPGAS for real time image processing in space , 2002, 2002 14th International Conference on Digital Signal Processing Proceedings. DSP 2002 (Cat. No.02TH8628).
[117] Gaye Lightbody,et al. Design of a parameterizable silicon intellectual property core for QR-based RLS filtering , 2003, IEEE Trans. Very Large Scale Integr. Syst..
[118] M. H. Supriya,et al. Gesture recognition using field programmable gate arrays , 2012, 2012 International Conference on Devices, Circuits and Systems (ICDCS).
[119] Jon A. Webb. Steps toward architecture-independent image processing , 1992, Computer.
[120] I. Yasri,et al. VLSI based edge detection hardware accelerator for real time video segmentation system , 2012, 2012 4th International Conference on Intelligent and Advanced Systems (ICIAS2012).