A novel on-chip electrostatic discharge protection design for RF ICs

Abstract A novel, compact electrostatic discharge (ESD) protection structure is designed, which protects integrated circuits (ICs) against ESD damages in all modes. This ultra-fast-response ESD structure, with response time of t 1 ∼0.16 nS, operates symmetrically. Measurements showed desired low holding voltage (∼2 V), low discharging impedance (

[1]  Albert Wang,et al.  A low-triggering circuitry for dual-direction ESD protection , 1999, Proceedings of the IEEE 1999 Custom Integrated Circuits Conference (Cat. No.99CH36327).

[2]  K. Narita,et al.  A novel on-chip electrostatic discharge (ESD) protection with common discharge line for high-speed CMOS LSIs , 1997 .

[3]  Albert Wang,et al.  A new design methodology using simulation for on-chip ESD protection designs for integrated circuits , 1998, 1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105).

[4]  E. A. Amerasekera,et al.  ESD in silicon integrated circuits , 1995 .

[5]  Albert Wang,et al.  A novel dual-direction IC ESD protection device , 1999, Proceedings of the 1999 7th International Symposium on the Physical and Failure Analysis of Integrated Circuits (Cat. No.99TH8394).