论文信息 - High Speed Hardware Computation of Co-evolution Models

High Speed Hardware Computation of Co-evolution Models

Field Programmable Gate Arrays (FPGAs) can provide the most suitable circuits for given problems by reconfiguring its circuits. In this paper, we show that a FPGA chip can achieve about 120 times of speedup compared with a workstation (Ultra-Sparc 200 MHz) in the computation of a co-evolution of strategies and scores in Iterated Prisoner's Dilemma game. This speedup makes it possible to challenge more complex problems beyond the limitation by software.

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