Triple patterning lithography (TPL) layout decomposition using end-cutting

Triple patterning lithography (TPL) is one of the most promising techniques in the 14nm logic node and beyond. However, traditional LELELE type TPL technology suffers from native conflict and overlapping problems. Recently LELEEC process was proposed to overcome the limitations, where the third mask is used to generate the end-cuts. In this paper we propose the first study for LELEEC layout decomposition. Conflict graphs and end- cut graphs are constructed to extract all the geometrical relationships of input layout and end-cut candidates. Based on these graphs, integer linear programming (ILP) is formulated to minimize the con ict number and the stitch number.

[1]  Burn J. Lin.  Lithography till the end of Moore's law , 2012, ISPD '12.

[2]  Bei Yu,et al.  Dealing with IC manufacturability in extreme scaling , 2012, ICCAD '12.

[3]  David Z. Pan,et al.  A high-performance triple patterning layout decomposer with balanced density , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[4]  Yao-Wen Chang,et al.  A novel layout decomposition algorithm for triple patterning lithography , 2012, DAC Design Automation Conference 2012.

[5]  David Z. Pan,et al.  Design for Manufacturing With Emerging Nanolithography , 2013, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[6]  Xin-She Yang,et al.  Introduction to Algorithms , 2021, Nature-Inspired Optimization Algorithms.

[7]  Kun Yuan,et al.  Layout Decomposition for Triple Patterning Lithography , 2015, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[8]  Peng Lei,et al.  Thermoelectric Heat Pump Drying Temperature Control System on the Basis of 89C51 , 2012, 2012 International Conference on Computer Science and Electronics Engineering.

[9]  Andrew B. Kahng,et al.  Layout decomposition for double patterning lithography , 2008, 2008 IEEE/ACM International Conference on Computer-Aided Design.

[10]  Yuelin Du,et al.  Constrained pattern assignment for standard cell based triple patterning lithography , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[11]  Kun Yuan,et al.  E-Beam Lithography Stencil Planning and Optimization With Overlapped Characters , 2012, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[12]  Puneet Gupta,et al.  A novel methodology for triple/multiple-patterning layout decomposition , 2012, Advanced Lithography.

[13]  David Z. Pan,et al.  L-shape based layout fracturing for e-beam lithography , 2013, 2013 18th Asia and South Pacific Design Automation Conference (ASP-DAC).

[14]  Zigang Xiao,et al.  A polynomial time triple patterning algorithm for cell based row-structure layout , 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[15]  Bei Yu,et al.  Implications of triple patterning for 14nm node design and patterning , 2012, Advanced Lithography.

[16]  Kun Yuan,et al.  Double Patterning Layout Decomposition for Simultaneous Conflict and Stitch Minimization , 2010, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[17]  Sani R. Nassif,et al.  ICCAD-2013 CAD contest in mask optimization and benchmark suite , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[18]  Hai Zhou,et al.  Layout decomposition with pairwise coloring for multiple patterning lithography , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[19]  Yue Xu,et al.  A matching based decomposer for double patterning lithography , 2010, ISPD '10.

[20]  Yinghai Lu,et al.  Post-routing layer assignment for double patterning , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[21]  C. Mack.  Fundamental principles of optical lithography : the science of microfabrication , 2007 .

[22]  Kun Yuan,et al.  A new graph-theoretic, multi-objective layout decomposition framework for Double Patterning Lithography , 2010, 2010 15th Asia and South Pacific Design Automation Conference (ASP-DAC).

[23]  Hajime Aoyama,et al.  EUV flare correction for the half-pitch 22nm node , 2010, Advanced Lithography.

[24]  Yih-Lang Li,et al.  TRIAD: A triple patterning lithography aware detailed router , 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[25]  David Z. Pan,et al.  Layout decomposition for quadruple patterning lithography and beyond , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[26]  Christopher P. Ausschnitt,et al.  Multi-patterning overlay control , 2008, SPIE Advanced Lithography.

[27]  Evangeline F. Y. Young,et al.  An efficient layout decomposition approach for Triple Patterning Lithography , 2013, 2013 50th ACM/EDAC/IEEE Design Automation Conference (DAC).

[28]  Martin D. F. Wong,et al.  Triple patterning aware routing and its comparison with double patterning aware routing in 14nm technology , 2012, DAC Design Automation Conference 2012.

[29]  David Z. Pan,et al.  Methodology for standard cell compliance and detailed placement for triple patterning lithography , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[30]  Christopher Cork,et al.  Comparison of triple-patterning decomposition algorithms using aperiodic tiling patterns , 2008, Photomask Japan.