A flexible algorithmic ADC for wireless sensor nodes

This paper presents the behavioral level modeling and circuit implementation of a flexible algorithmic ADC that can be used for Bluetooth and CDMA2000-1X receivers, and sensor applications. An accurate behavioral level model of the ADC has been implemented in Matlab/Simulink, including the most important circuit non-idealities. This model allows exhaustive behavioral simulations, to achieve an optimal design. The accurate behavioral model shows that a dynamic range of 60 dB can be achieved for a bandwidth up to 1.25 Mega Samples Per Second (MSPS), which is sufficient for Bluetooth and CDMA2000-1X standards, and medium resolution sensors. The highest achievable sampling rate is 2.8 MSPS. The transistor level implementation of the ADC in a 0.35 mum CMOS process shows that the analog part of the ADC consumes 11 mW of power from a 3.3 V supply.

[1]  M. Ismail,et al.  A low power multi-standard sigma-delta ADC for WCDMA/GSM/Bluetooth applications , 2004, The 2nd Annual IEEE Northeast Workshop on Circuits and Systems, 2004. NEWCAS 2004..

[2]  Kristofer S. J. Pister,et al.  An ultralow-energy ADC for Smart Dust , 2003, IEEE J. Solid State Circuits.

[3]  Khurram Muhammad,et al.  A sigma-delta ADC with a built-in anti-aliasing filter for Bluetooth receiver in 130nm digital process , 2004, Proceedings of the IEEE 2004 Custom Integrated Circuits Conference (IEEE Cat. No.04CH37571).

[4]  W. C. Black,et al.  Sub-sampling sigma-delta modulator for baseband processing , 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).

[5]  Paul R. Gray,et al.  A 10 b, 20 Msample/s, 35 mW pipeline A/D converter , 1995, IEEE J. Solid State Circuits.

[6]  S. H. Lewis,et al.  A pipelined 5-Msample/s 9-bit analog-to-digital converter , 1987 .

[7]  Andrea Baschirotto,et al.  Behavioral modeling of switched-capacitor sigma-delta modulators , 2003 .

[8]  Per Lindgren,et al.  A Bluetooth-based Sensor Node for Low-Power Ad Hoc Networks , 2008, J. Comput..

[9]  E. Sanchez-Sinencio,et al.  A 10-bit 44-MS/s 20-mW configurable time-interleaved pipeline ADC for a dual-mode 802.11b/Bluetooth receiver , 2006, IEEE Journal of Solid-State Circuits.

[10]  Mohammed Ismail,et al.  Behavioral Modeling of a Programmable UWB/Bluetooth ADC , 2007, 2007 14th IEEE International Conference on Electronics, Circuits and Systems.

[11]  R.H.M. van Veldhoven.  A triple-mode continuous-time /spl Sigma//spl Delta/ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver , 2003 .

[12]  D. Everitt,et al.  An Interoperability Framework for Sensor and UMTS Networks , 2007, 2007 Third International Conference on Wireless and Mobile Communications (ICWMC'07).

[13]  Gernot Hueber,et al.  A Single-Chip Dual-Band CDMA2000 Transceiver in 0.13 $\mu{\hbox{m}}$ CMOS , 2007, IEEE Journal of Solid-State Circuits.

[14]  R. V. Veldhoven.  A triple-mode continuous-time ΣΔ modulator with switched-capacitor feedback DAC for a GSM-EDGE/CDMA2000/UMTS receiver , 2003, IEEE J. Solid State Circuits.

[15]  R. Tielert,et al.  A 0.11mm/sup 2/ low-power A/D-converter cell for 10b 10MS/s operation , 2004, Proceedings of the 30th European Solid-State Circuits Conference.