Automatic test point insertion for pseudo-random testing

A combination of techniques for efficiently inserting test points is proposed. These techniques refer to three complementary abstraction levels: algorithms, circuits, and layout. The authors deal with pseudo-random testing and present a method of condensing test points based on the notion of fault sector. Based on a set of proposed heuristics, a tool for automatically inserting test points was developed. Experimental results obtained with the tool are presented to indicate that excellent pseudo-random testability can be achieved with few test points. This technique leads to the lowest reported number of test points while significantly reducing the number of random patterns which are required to achieve very close to 100% fault coverage.<<ETX>>

[1]  Jacob Savir,et al.  Built In Test for VLSI: Pseudorandom Techniques , 1987 .

[2]  J. R. Fox Test-point Condensation in the Diagnosis of Digital Circuits , 1977 .

[3]  Y. Savaria,et al.  Force-observe, a new design for testability approach (CMOS VLSI circuits) , 1988, 1988., IEEE International Symposium on Circuits and Systems.

[4]  T. Gheewala,et al.  CrossCheck: A Cell Based VLSI Testability Solution , 1989, 26th ACM/IEEE Design Automation Conference.

[5]  Robert Hum,et al.  Applications of Testability Analysis: From ATPG to Critical Delay Path Tracing , 1984, ITC.

[6]  John P. Hayes On Modifying Logic Networks to Improve Their Diagnosability , 1974, IEEE Transactions on Computers.

[7]  Arthur D. Friedman,et al.  Test Point Placement to Simplify Fault Detection , 1974, IEEE Transactions on Computers.

[8]  Daniel Brand,et al.  Synthesis of pseudo-random pattern testable designs , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.

[9]  Andrzej Krasniewski,et al.  Circular Self-Test Path: A Low-Cost BIST Technique , 1987, 24th ACM/IEEE Design Automation Conference.

[10]  A. J. Briers,et al.  Random Pattern Testability by Fast Fault Simulation , 1986, International Test Conference.

[11]  F. Brglez,et al.  A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN , 1985 .

[12]  B. Koenemann,et al.  Built-in logic block observation techniques , 1979 .

[13]  Yvon Savaria,et al.  A pragmatic approach to the design of self-testing circuits , 1989, Proceedings. 'Meeting the Tests of Time'., International Test Conference.