An improved direct boundary element method for substrate coupling resistance extraction

It is important to model the substrate coupling for mixed-signal circuit designs today. This paper presents an improved direct boundary element method (DBEM) for substrate resistance calculation, where only the boundary of substrate volumes is discretized and only the free-space Green function is used. At first, we discard some inessential unknowns to compress the linear system without accuracy loss. Then we make the coefficient matrix sparser. In this way, solving the linear system is greatly accelerated. Experiments on various substrates validate that DBEM is several to tens of times faster than DCT-accelerated Green's function methods and the eigendecomposition method, while preserving high accuracy. Besides, another experiment shows that this method is versatile for irregular substrates.

[1]  Ali M. Niknejad,et al.  Numerically stable Green function for modeling and analysis of substrate coupling in integrated circuits , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[2]  Xavier Aragones,et al.  Analysis and Solutions for Switching Noise Coupling in Mixed-Signal ICs , 1999 .

[3]  Wenjian Yu,et al.  Enhanced QMM-BEM solver for three-dimensional multiple-dielectric capacitance extraction within the finite domain , 2004, IEEE Transactions on Microwave Theory and Techniques.

[4]  E. Schrik,et al.  Combined BEM/FEM substrate resistance modeling , 2002, Proceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324).

[5]  Robert G. Meyer,et al.  Analysis and simulation of substrate coupling in integrated circuits , 1995, Int. J. Circuit Theory Appl..

[6]  Zeyi Wang,et al.  CAPACITANCE EXTRACTION , 2004 .

[7]  João Paulo Costa,et al.  Efficient techniques for accurate modeling and simulation of substrate coupling in mixed-signal IC's , 1998, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[8]  Luis Miguel Silveira,et al.  Characterizing substrate coupling in deep-submicron designs , 2002, IEEE Design & Test of Computers.

[9]  Jacob K. White,et al.  FastCap: a multipole accelerated 3-D capacitance extraction program , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[10]  Robert G. Meyer,et al.  Modeling and analysis of substrate coupling in integrated circuits , 1996 .

[11]  Edoardo Charbon,et al.  Substrate coupling: modeling, simulation and design perspectives , 2004, International Symposium on Signals, Circuits and Systems. Proceedings, SCS 2003. (Cat. No.03EX720).

[12]  Weiping Shi,et al.  A fast hierarchical algorithm for three-dimensional capacitanceextraction , 2002, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[13]  Wenjian Yu,et al.  Enhanced QMM-BEM solver for three-dimensional multiple-dielectric capacitance extraction within the finite domain , 2004 .

[14]  Mattan Kamon,et al.  FastHenry: A Multipole-Accelerated 3-D Inductance Extraction Program , 1993, 30th ACM/IEEE Design Automation Conference.

[15]  Wenjian Yu,et al.  Fast capacitance extraction of actual 3-D VLSI interconnects using quasi-multiple medium accelerated BEM , 2003 .

[16]  K. Joardar,et al.  Signal isolation in BiCMOS mixed mode integrated circuits , 1995, Proceedings of Bipolar/Bicmos Circuits and Technology Meeting.

[17]  Wenjian Yu,et al.  Substrate resistance extraction with direct boundary element method , 2005, Proceedings of the ASP-DAC 2005. Asia and South Pacific Design Automation Conference, 2005..

[18]  Jacob K. White,et al.  Algorithms in FastImp: a fast and wideband impedance extraction program for complicated 3-D geometries , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[19]  Zeyi Wang,et al.  A two-dimensional resistance simulator using the boundary element method , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Y. Saad,et al.  GMRES: a generalized minimal residual algorithm for solving nonsymmetric linear systems , 1986 .

[21]  R. B. Iverson,et al.  A stochastic algorithm for high speed capacitance extraction in integrated circuits , 1992 .

[22]  Chi-Yuan Lo,et al.  Parasitic extraction: current state of the art and future trends , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[23]  Iain S. Duff,et al.  On Algorithms For Permuting Large Entries to the Diagonal of a Sparse Matrix , 2000, SIAM J. Matrix Anal. Appl..

[24]  Jacob K. White,et al.  A precorrected-FFT method for electrostatic analysis of complicated 3-D structures , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[25]  Weiping Shi,et al.  A divide-and-conquer algorithm for 3-D capacitance extraction , 2004, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[26]  N. P. van der Meijs,et al.  Combined BEM/FEM substrate resistance modeling , 2002, DAC '02.

[27]  Mohamed I. Elmasry,et al.  A novel analytical model for evaluation of substrate crosstalk in VLSI circuits , 2002, Proceedings First IEEE International Workshop on Electronic Design, Test and Applications '2002.

[28]  Kai Chang,et al.  Encyclopedia of RF and microwave engineering , 2005 .

[29]  Lawrence T. Pileggi,et al.  Inductance 101: modeling and extraction , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[30]  Robert G. Meyer,et al.  Modeling and analysis of substrate coupling in integrated circuits , 1995, Proceedings of the IEEE 1995 Custom Integrated Circuits Conference.

[31]  N.P. van der Meijs,et al.  Extraction of circuit models for substrate cross-talk , 1995, Proceedings of IEEE International Conference on Computer Aided Design (ICCAD).

[32]  N. P. van der Meijs,et al.  Extraction of circuit models for substrate cross-talk , 1995, ICCAD.