Traffic management circuit for the shared buffer memory switch with multicasting

The shared buffer memory switch has some merits such as higher bandwidth utilization and lower buffer size. It can also be modified to perform multicasting, but the multicasting cells have a higher priority to be switched. The traffic management circuit (TMC) we propose in this paper can solve this unfair problem by properly allocating the throughputs of both multicasting and general cells. The formulae for setting the control parameter in TMC are also derived.

[1]  Hiroshi Kuwahara,et al.  Shared buffer memory switch for an ATM exchange , 1993, IEEE Trans. Commun..

[2]  Hiroshi Kuwahara,et al.  A shared buffer memory switch for an ATM exchange , 1989, IEEE International Conference on Communications, World Prosperity Through Communications,.

[3]  Takahiko Kozaki,et al.  32 x 32 Shared Buffer Type ATM Switch VLSI's for B-ISDN's , 1991, IEEE J. Sel. Areas Commun..

[4]  Fouad A. Tobagi,et al.  Fast packet switch architectures for broadband integrated services digital networks , 1990, Proc. IEEE.

[5]  Shoichi Shimizu,et al.  A One-Chip Scalable 8 * 8 ATM Switch LSI Employing Shared Buffer Architecture , 1991, IEEE J. Sel. Areas Commun..

[6]  Y. Sakurai,et al.  Large-scale ATM multistage switching network with shared buffer memory switches , 1991, IEEE Communications Magazine.