WPM 3.7: A 90MHz CMOS RISC CPU Designed for Sustained Performance

This CMOS CPU operates at 90MHz under typical conditions. lL implements an existing RISC 140-instr uction set I 'The pro­ cessor has been designed for suslained performance for work­ slation and both commerical and technical multisuer applica­ tions. Key performance features include a 3ns 32-bit adder, low-skew on-chip clock buffers, and cycling off-chip caches at the operating frequency using industry-standar d synchronous SRAMS. The speeds obta ined are comparable to those of many ECL implementations. The CPU chip includes the following hardware: inleger fetch and execute unit, on-chip split I/D TLBs with 2-way 64 entries each, control for second-level off-chip TLBs, conlrol for off-chip 2-way split I/D writeback caches with single-bit error correction for data, full multiprocessing support hardware, interface for performance analysis and tuning, and a tightly­ coupled co-processor interface.