Development of high resolution TDC ASICs at GSI

Based on the long experience on high precision time measurement systems at GSI the GSI ASIC design group is developing a new TDC ASIC for CBM one of the next generation large scale experiments at GSI. The main requirement on the TDC is the high timing resolution < 20 ps. The data acquisition architecture has to be event driven. Two approaches for this TDC are under evaluation. One approach is a time to amplitude converter (TAC) core which is successfully implemented in former GSI experiments. The other one is a DLL based TDC. For both approaches test chips had been designed and measurement results are already available. These results will be presented in detail. Furthermore in the presentation the next steps towards a high precision TDC fitting into the CBM TOF environment will be discussed.