Method and apparatus correcting digital error of successive approximation analog to digital converter

The present invention relates to a technique of improving the A / D conversion speed using digital error correction techniques in the SAR-ADC and ease the design requirements of a reference voltage driver. The present invention is a process for managing the DAC, set the array of elements for generating an analog signal into a plurality of sub-DAC, and is composed of one they share one or more elements form to generate a compare reference voltage of the input signal and .; When generating the DAC signal that is the basis for the comparison with the first input signal to obtain a digital output code of the input signal through the DAC, by applying an intended offset for the digital error correction in later gaining MSB, after which the process of obtaining the digital output code in such a way that by applying a binary decision technique obtains the code of the sub-bit sub-DAC and sequentially; At the start of the code determined by the sub-DAC of the next stage to share the sub-DAC and the element, and switching back to the DAC elements used to determine the parent code will place the range expected at the level of an analog input voltage with no additional element redundancy the process of expansion and, obtain a digital output code in accordance with the SAR binary decision process over a low-order bit from the DAC elements to be shared after the comparison voltage is generated in the center of the range and; In addition to be superposed to the output code is obtained by using the output code, and then sub-DAC is obtained by means of the sub-DAC is achieved by a process for outputting the result to the end of the digital output code. A / D converter, digital error correction, the sub-DAC