Design of Double SDRAM Controller for Multibus Ground-Based Test Equipment
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A double Synchronous Dynamic Random Access Memory controller based on ping-pong operation as the data buffer is designed to meet the requirement of large data amount and high transmission speed for multibus ground-based test equipment of a certain missile system. The design scheme which use FPGA as the main controller is presented in detail, including the internal interface of SDRAM, processings of data transmission and realization of ping-pong operation. The function of this controller is validated through the picked images from image generator, and the result shows that it can write and read data at the steady rate of 125Mbit/s, which indicate this SDRAM controller is feasible for the multibus ground-based test equipment
[1] Guo Li. The Feature of DDR SDRAM and the Implementation of DDR SDRAM Controllers via VHDL , 2002 .
[2] Wu,et al. Design and implementation of an efficient SDRAM controller for HDTV decoder , 2007 .
[3] Zhu Xin-ping. Design of Video Multi-function Board Based on CPLD and SDRAM , 2009 .
[4] Sun Rui. A Research of Basic Structure Operations and Relative Timing Parameters of SDRAM , 2010 .
[5] M. Brox,et al. A Comparison of current SDRAM types: SDR, DDR, and RDRAM , 2003 .