Two Behavioural Error Detection Techniques for the Cascaded Integrator–Comb Interpolation Filter Implemented on FPGA

[1]  L. Rabiner,et al.  Optimum FIR Digital Filter Implementations for Decimation, Interpolation, and Narrow-Band Filtering , 1975 .

[2]  M. Re,et al.  Digital modulator architectures for satellite and space applications , 2002, ICCSC'02. 1st IEEE International Conference on Circuits and Systems for Communications. Proceedings (IEEE Cat. No.02EX605).

[3]  E. Hogenauer,et al.  An economical class of digital filters for decimation and interpolation , 1981 .

[4]  M. Luise,et al.  Digital satellite receiver for wideband multi-rate Ka-band communications , 2007, IEEE Transactions on Aerospace and Electronic Systems.

[5]  R. Bhakthavatchalu,et al.  Design of optimized CIC decimator and interpolator in FPGA , 2013, 2013 International Mutli-Conference on Automation, Computing, Communication, Control and Compressed Sensing (iMac4s).

[6]  Mladen Vucic,et al.  Closed-Form Design of CIC Compensators Based on Maximally Flat Error Criterion , 2011, IEEE Transactions on Circuits and Systems II: Express Briefs.

[7]  L. Rabiner,et al.  Further considerations in the design of decimators and interpolators , 1976 .

[8]  L. Rabiner,et al.  A novel implementation for narrow-band FIR digital filters , 1975 .

[9]  G. Jovanovic-Dolecek.  Efficient technique for improving the frequency response of CIC decimation filter , 2005, IEEE International Symposium on Communications and Information Technology, 2005. ISCIT 2005..

[10]  Alfonso Fernández-Vázquez,et al.  Maximally Flat CIC Compensation Filter: Design and Multiplierless Implementation , 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

[11]  Ian McLoughlin,et al.  Fault tolerance through redundant COTS components for satellite processing applications , 2003, Fourth International Conference on Information, Communications and Signal Processing, 2003 and the Fourth Pacific Rim Conference on Multimedia. Proceedings of the 2003 Joint.