Design of CMOS differential LNA at 2.4GHz

This paper present design and simulation of differential low noise amplifier that utilized inductively degenerated common-source (CS) open drain cascode topology. The operating frequency for the design was at 2.4GHz for IEEE 802.11b standard. The LNA has been implemented in RF 0.13um CMOS process. Power constraint noise optimization method has been used to obtain the optimized width of the transistor with a low noise figure and good power gain. Post layout simulation provides a forward gain (S21) of 18.56dB, S11 of -27.63dB with a noise figure (NF) of 1.85dB and IIP3 = -7.75. The total current consumed by the circuit is 7.59mA thus making the power consumption is 9mW.

[1]  Yingmei Chen,et al.  A CMOS Single-Differential LNA and current bleeding CMOS mixer for GPS Receivers , 2010, 2010 IEEE 12th International Conference on Communication Technology.

[2]  N.M. Noh,et al.  Design, Simulation and Measurement Analysis on the S-parameters of an Inductively-degenerated Common-source Open-drain Cascode Low Noise Amplifier , 2007, 2007 IEEE International Workshop on Radio-Frequency Integration Technology.

[3]  Thomas H. Lee,et al.  The design and implementation of low-power CMOS radio receivers , 1999 .

[4]  R. Castello,et al.  A 2-dB noise figure 900-MHz differential CMOS LNA , 2001 .

[5]  Trung-Kien Nguyen,et al.  CMOS low-noise amplifier design optimization techniques , 2004, IEEE Transactions on Microwave Theory and Techniques.

[6]  Heng Zhang,et al.  A Noise Reduction and Linearity Improvement Technique for a Differential Cascode LNA , 2008, IEEE Journal of Solid-State Circuits.