Specification and properties of a cache coherence protocol model

This paper describes a cache coherence protocol for an architecture composed of several processors, each with their own local cache, connected via a switching structure to a shared memory itself split into several modules managed by independent controllers. The protocol prevents processors from simultaneously modifying their respective copies and always provides a processor requiring a copy of a memory location with the most up-to-date version. A top down description and modeling of the protocol is given using Predicate/Transition nets. This modeling allows to formally describe the complex synchronizations of this protocol. Then invariants are directly obtained without unfolding the Predicate/Transition net. They are the basis for studying behavioral properties.

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