Quantification and mitigation strategies of neutron induced soft-errors in CMOS devices and components

As semiconductor device scaling is on-going far below 100nm design rule, terrestrial neutron-induced soft-error typically in SRAMs is predicted to be worsen furthermore. Moreover, novel failure modes that may be more serious than those in memory soft-error are recently being reported. Therefore, necessity of implementing mitigation techniques is rapidly growing at the design phase, together with development of advanced detection and quantification techniques. The most advanced such techniques are reviewed and discussed.

[1]  S. S. Chung,et al.  Spreading Diversity in Multi-cell Neutron-Induced Upsets with Device Scaling , 2006, IEEE Custom Integrated Circuits Conference 2006.

[2]  R. Tsuchiya,et al.  Comprehensive study on vth variability in silicon on Thin BOX (SOTB) CMOS with small random-dopant fluctuation: Finding a way to further reduce variation , 2008, 2008 IEEE International Electron Devices Meeting.

[3]  E. Ibe,et al.  Impact of Scaling on Neutron-Induced Soft Error in SRAMs From a 250 nm to a 22 nm Design Rule , 2010, IEEE Transactions on Electron Devices.

[4]  Trevor Mudge,et al.  Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[5]  peixiong zhao,et al.  Impact of Low-Energy Proton Induced Upsets on Test Methods and Rate Predictions , 2009, IEEE Transactions on Nuclear Science.

[6]  T. Calin,et al.  Upset hardened memory design for submicron CMOS technology , 1996 .

[7]  Yuki Yoshikawa,et al.  An FPGA-based fail-soft system with adaptive reconfiguration , 2010, 2010 IEEE 16th International On-Line Testing Symposium.

[8]  Taiki Uemura,et al.  Using Low Pass Filters in Mitigation Techniques against Single-Event Transients in 45nm Technology LSIs , 2008, 2008 14th IEEE International On-Line Testing Symposium.

[9]  Shigetaka Kumashiro,et al.  Measurement of neutron-induced single event transient pulse width narrower than 100ps , 2010, 2010 IEEE International Reliability Physics Symposium.

[10]  Ivan R. Linscott,et al.  LEAP: Layout Design through Error-Aware Transistor Positioning for soft-error resilient sequential cell design , 2010, 2010 IEEE International Reliability Physics Symposium.

[11]  T. D. Loveless,et al.  A Single-Event-Hardened Phase-Locked Loop Fabricated in 130 nm CMOS , 2007, IEEE Transactions on Nuclear Science.

[12]  T.M. Mak,et al.  Built-In Soft Error Resilience for Robust System Design , 2007, 2007 IEEE International Conference on Integrated Circuit Design and Technology.

[13]  L.W. Massengill,et al.  Simultaneous single event charge sharing and parasitic bipolar conduction in a highly-scaled SRAM design , 2005, IEEE Transactions on Nuclear Science.

[14]  Jaume Segura,et al.  Cross-BIC architecture for single and multiple SEU detection enhancement in SRAM memories , 2010, 2010 IEEE 16th International On-Line Testing Symposium.

[15]  M. Cabanas-Holmen,et al.  Heavy Ion and High Energy Proton-Induced Single Event Transients in 90 nm Inverter, NAND and NOR Gates , 2009, IEEE Transactions on Nuclear Science.

[16]  T. Makino,et al.  Soft-Error Rate in a Logic LSI Estimated From SET Pulse-Width Measurements , 2009, IEEE Transactions on Nuclear Science.

[17]  S. Rezgui,et al.  New Methodologies for SET Characterization and Mitigation in Flash-Based FPGAs , 2007, IEEE Transactions on Nuclear Science.

[18]  Sarita V. Adve,et al.  SWAT : An Error Resilient System , 2008 .

[19]  Kazutoshi Kobayashi,et al.  An Area/Delay Efficient Dual-Modular Flip-Flop with Higher SEU/SET Immunity , 2010, IEICE Trans. Electron..

[20]  Kazutoshi Kobayashi,et al.  A 65nm Bistable Cross-coupled Dual Modular Redundancy Flip-Flop capable of protecting soft errors on the C-element , 2010, 2010 Symposium on VLSI Circuits.

[21]  Eishi Ibe,et al.  Novel SER standards: Backgrounds and methodologies , 2010, 2010 IEEE International Conference on Integrated Circuit Design and Technology.

[22]  M.D. Berg,et al.  Single-Event Upsets and Multiple-Bit Upsets on a 45 nm SOI SRAM , 2009, IEEE Transactions on Nuclear Science.

[23]  H. Puchner,et al.  Investigation of multi-bit upsets in a 150 nm technology SRAM device , 2005, IEEE Transactions on Nuclear Science.

[24]  Norbert Seifert,et al.  Soft Error Rates of Hardened Sequentials utilizing Local Redundancy , 2008, 2008 14th IEEE International On-Line Testing Symposium.

[25]  Shimbo Kenichi,et al.  Correlation of Mitigation of Soft-error Rate of Routers between Neutron Irradiation Test and Field Soft-error Data , 2009 .

[26]  L. Borucki,et al.  Comparison of accelerated DRAM soft error rates measured at component and system level , 2008, 2008 IEEE International Reliability Physics Symposium.

[27]  Raoul Velazco,et al.  Two CMOS memory cells suitable for the design of SEU-tolerant VLSI circuits , 1994 .

[28]  Eishi Ibe,et al.  Panel: SER standards: Where we are? what's next? , 2010, 2010 IEEE 16th International On-Line Testing Symposium.

[29]  Takashi S. Nakamura,et al.  Terrestrial Neutron-Induced Soft Errors in Advanced Memory Devices , 2008 .

[30]  Nobuyasu Kanekawa,et al.  Dependability in Electronic Systems: Mitigation of Hardware Failures, Soft Errors, and Electro-Magnetic Disturbances , 2010 .

[31]  Yusuke Matsunaga,et al.  A robust algorithm for pessimistic analysis of logic masking effects in combinational circuits , 2011, 2011 IEEE 17th International On-Line Testing Symposium.

[32]  K.C. Mohr,et al.  Optimizing Radiation Hard by Design SRAM Cells , 2007, IEEE Transactions on Nuclear Science.

[33]  Jr. Leonard R. Rockett.  An SEU-hardened CMOS data latch design , 1988 .

[34]  A. Lesea,et al.  Experimental study and analysis of soft errors in 90nm Xilinx FPGA and beyond , 2007, 2007 9th European Conference on Radiation and Its Effects on Components and Systems.

[35]  Eishi Ibe.  Scaling Effects on Neutron-Induced Soft Error in SRAMs Down to 22 nm Process S , 2009 .

[36]  T. Skotnicki,et al.  Impact of the lateral source/drain abruptness on MOSFET characteristics and transport properties , 2003, IEEE International Electron Devices Meeting 2003.

[37]  Keiji Takahisa,et al.  SEILA: Soft error immune latch for mitigating multi-node-SEU and local-clock-SET , 2010, 2010 IEEE International Reliability Physics Symposium.

[38]  A. KleinOsowski,et al.  Clock and Reset Transients in a 90 nm RHBD Single-Core Tilera Processor , 2009, IEEE Transactions on Nuclear Science.

[39]  Dimitris Gizopoulos,et al.  A software-based self-test methodology for in-system testing of processor cache tag arrays , 2010, 2010 IEEE 16th International On-Line Testing Symposium.

[40]  Farid N. Najm,et al.  A Soft-Error Tolerant Content-Addressable Memory (CAM) Using An Error-Correcting-Match Scheme , 2006, IEEE Custom Integrated Circuits Conference 2006.